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Timing Problem in Video Image Processing Reference Design

Altera_Forum
Honored Contributor II
769 Views

Hi, 

 

I'm trying to implement Reference Design of VIP on Cyclone 3 development board. The version of Quartus is 11.1. I unzipped the design that I downloaded it from the altera web site. Then compile it without any change. Timing constraints was not met at the end of compile operation. what should I do to meet the requirements? When I see the results, I hesitated. This is a reference for us, but not work properly. 

 

In fact, I'm trying to get 1080p dvi data and scale it to 1024x768 resolution and sent it through dvi out. The sequence in my project is: 

 

clocked video input -> video frame buffer -> scaler -> mixer -> video frame buffer -> clocked video output. 

 

I used 2 pipeline bridges for both frame buffers separately. I used ddr sdram in full rate. It's clock rate is 125 Mhz. When I compile it, the timing was not met? Is there any recommendation? Is the flow true? 

 

Thanks. 

 

Aziz
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