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Timing constraints for Stratix IV ALTGX transceiver block

Altera_Forum
Honored Contributor I
969 Views

Hi, 

What timing constraints do I need to provide so that the high-speed transceiver ALTGX block can work correctly? 

 

I have constrained the input refclk. 

I have used "derive_pll_clocks", which then generates a bunch of clocks both on the Tx and the Rx side. 

 

But is this enough to constrain the timing for my FPGA-Tranceiver interface? I am using the PMA-direct mode. Do I need to specifically constrain the interface clocks with an additional create_clock statement? 

 

I have search on this forum and the web, but I haven't found anyone addressing this issue. If you could point me towards the answer, it would be much appreciated.
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Altera_Forum
Honored Contributor I
83 Views

Hello. 

 

I am beginning to study Stratix-IV and I have the same question. 

 

I am trying to use ALTGX on Stratix-IV. So I make a project with ALTGX and trying to compile it. 

 

There are two ways for me now: 

 

1) I make constraints for input frequencies and put "derive_pll_clocks" in .sdc file. Quartus V11 successfully compile my project without warnings or messages about unconstrained paths. 

 

2) When I create/update .sdc file in TimeQuest, it adds multiple constraints in this .sdc file that concerns ALTGX. 

 

If I compile my project with such .sdc file, about 30 warnings appear. Also unconstrained pathes appeared. 

It seems to me that constraints that TimeQuest generate for ALTGX, do not correspond to my own implementation of ALTGX... 

 

So there is a question, how to make proper constraints for ALTGX? Is the way 1) good for using, or I should make TimeQuest' constraints to work good? 

 

Are there some Application Note for ALTGX constraining? 

 

Thank you in advance.
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