Timing for PLL clock PLL_RECONFIG~FMAX_CAP_FF

[K_Crocker]

Each PLL instantiated in my design has a PLL_RECONFIG~FMAX_CAP_FF clock that isn't constrained. Can I constrain these clocks, and, if so, what frequency value should I use? TIA for your answer!

[RichardTanSY_Altera]

Which device are you using?

Kindly share your design by archiving the project (Project > Archive Project) so that I can investigate it further.

Regards,

Richard Tan

[RichardTanSY_Altera]

Hi,

Do you able to share the design with us?

Regards,

Richard Tan

[K_Crocker · Accepted solution]

Hi Richard,

The design is quite large, so I can't share it. But to the point, the error is within the Reconfigurable PLL IP block. I think it has to do with the strange timing of the "phase_done" signal, which I believe I have accounted for after carefully reading the user guide. I was hoping that you might have some special knowledge from seeing this condition before.

So, that said, I think I'll false path or underconstrain the "clock" to get around the issue and close out this request. Thank you for your help.

[RichardTanSY_Altera]

Noted. If you encounter any further issues, feel free to submit a new case for support.

You may also consider creating a simplified design to replicate the issue.

Now, I will transitioning this thread to community support. If you have any further questions or concerns, please don't hesitate to reach out. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support.

The community users will be able to help you on your follow-up questions.

Thank you and have a great day!

Best Regards,

Richard Tan