I am trying to tap a working video design that captures live video from a CCD camera and displays it on the lcd. As, Quartus v12 provides IPs for tapping avalon-ST data i.e. avalon-ST video monitor and trace system megacore functions so i used them. BUT when when I synthesize my new design, it generates following error:--- Quote Start --- Error (10228): Verilog HDL error at altera_avalon_st_pipeline_base.v(22): module "altera_avalon_st_pipeline_base" cannot be declared more than once --- Quote End --- As far as i get it, module name "altera_avalon_st_pipeline_base" is getting repeated within the project but the path for "altera_avalon_st_pipeline_base.v" is --- Quote Start --- project directory\trace_system_1\ altera_jtag_dc_streaming\altera_avalon_st_pipeline_base.v --- Quote End --- ...which indicates that error lies in trace system megacore generated files. does anybody have a clue how to fix this???
I'm trying to guess what might be wrong with your system but I'm guessing so please confirm that I've guessed right.
Is it possible to upgrade your project to QSYS? I suspect that if you do that will fix the problem.If not then please check that the two copies of the pipeline_base.v file are the same. If they are then deleting one of them should make the design compile. I really do recommend upgrading to QSYS unless you have good reasons why not though, as it's possible that you'll hit problems later on with SOPCB.
Unfortunately, it is not possible to upgrade to Qsys currently due to shortage of time. Nevertheless, I have deleted the redundant copies of same file and project gets compiled. BUT when i load my design in system console it doesn't detect trace system module...any ideas??