Transceiver Native PHY clock and data width

[MaCo]

Hello, I configured the Transceiver Native PHY for a Cyclone V GX design to 2500 Mbps and enabled the simplified data interface so that I get a 32 bit data interface for tx and rx. The measured clocks (rx_std_clkout and tx_std_clkout) of the PCS interface have 62.5 MHz. 62.5 Mhz * 32 bit is not equal to 2500 Mbps. What am I doing wrong or what am I missing !?!?!?

[Kshitij_Intel]

Hi,

It could be due to 8b/10b encoding. For 32bit, there will be 40bits and 62.5*40 = 2500.

Hope it clarifies now.

Thank you,

Kshitij Goel

[Kshitij_Intel · Accepted solution]

Hi,

As we do not receive any response from you on the previous answer that we have provided. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.

Thank you,

Kshitij Goel

[MaCo]

Hi Intel guys,

just a remark, I can't press the "Accept as solution" button using Firefox under Ubuntu 2020.2 LTS, got only an error message.