Transceiver Native PHY simulation error

[Kavin]

I got some problems in simulating  Native PHY recently,after compiling  all the necessary design files, i can not excute simulation due to following errors:

how to solve these errors,and any suggestions on Native PHY simulation?

Thanks

Kavin

[CheePin_C_Intel]

Hi Kavin,

As I understand it, you encounter some issue running simulation with Native PHY. As I look at the screenshot, seems like the simulation error is related to the reset controller module. Would you mind to further elaborate on the specific steps that you are taking to compile the reset controller libraries and the files that you have compiled?

Just wonder if you have had a chance to try the following:

1. Try with other Quartus version ie the latest Q20.2Pro to see if similar issue occurs to narrow down Quartus version dependent issue.

2. I notice that you seems to be using simulator tool other than Modelsim. Would you mind to try with Modelsim AE to see if similar issue occurs to narrow down to simulator tool dependent issue.

Please let me know if there is any concern. Thank you.

Best regards,
Chee Pin

[Kavin]

Hi Chee Pin，

Glad to hear you.I use Questasim 10.2c to simulate Native PHY on Arria 10 deveices.When the IP is successfully generated, a folder named sim will be generated in the root directory. When compiling the simulation library, I compiled all the HDL files in the sim folder, and the compilation results showed that they were successful. Then I generated the simulation file to start the simulation, and the errors mentioned before appeared. I also tried to compile according to the order of loading files when QSYS was compiled, but it did not improve.

1.I have tried both versions of quartus 17.1 and 18.1, but there is no improvement. License will be a problem for 20.2;

2.Qustasim is nearly the same with Modelsim,but I will try with Modelsim latest version. 

3.Is it possible for you to help me use the latest version of quartus to generate a Native PHY design example so that I can use it to check my simulation problems.

Best regards,
Kavin

[Kavin]

The following is my native phy design ，it may helps.

[CheePin_C_Intel]

Hi,

Please correct me if I am wrong, as I understand it, you configure your settings in Native PHY IP Parameter Editor and generate the HDL with simulation model. Then you go to the sim folder to compile and run the simulation. For your information, for the simulation to work, you will need to hook up additional IPs ie XCVR reset controller and the TX PLL.

I have a A10 Native PHY simulation example previously from wiki but it is running on Q15.1. You can refer to it and try to customize from there.

Thank you.

[Kavin]

Hi

Both XCVR reset controller and tx pll were added in my design.I can not find your simulation example, could you be kind enough to e_mail the example to me?

Thanks

Kavin

[CheePin_C_Intel]

Hi,

I have resend the file to your Forum registered email, using forum as well as using my company email. Please let me know if you still do not receive it. Thank you.

[Kavin]

Hi

Thanks.I received your email last week.With your help,i can simulate now,but i found rx_parallel_data is not the same as tx_parallel_data,is there any specifical rules i should follow? If 8B/10B coder is not applied, rx_parallel_data should be exactly the same as tx_parallel_data,is it right?

Thanks

Kavin

[CheePin_C_Intel]

Hi,

Thanks for your update. Regarding the parallel data mismatch, for your information, to ensure the parallel data is matching, you would need to perform the word alignment. Just wonder if you have had a chance to look into word alignment? Are you running the simulation with the example design which I shared or your own design currently?

Thank you.

[Kavin]

Hi

Thanks.I used to think that word alignment is done automatically by PHY. At your reminder,  the simulation goes well after word alignment. Do all types of PHYs do not support automatic alignment, and does the actual design require internal logic for byte alignment?

Thanks

[CheePin_C_Intel · Accepted solution]

Hi,

For your information, the Native PHY can perform automatic word alignment if the RX word aligner mode is configured to “synchronous state machine”. I believe the example that you are having might be using manual alignment mode.

Sorry for the inconvenience.

Best regards,

Chee Pin

[Kavin]

Hi

Thanks.I am using "bitslip" mode now,and i will try with “synchronous state machine”.Thanks for your help in recent days.

Best regards,

Kavin

[CheePin_C_Intel]

Hi Kavin,

Thanks for your update. You are most welcome.

[CheePin_C_Intel]

Hi,

I believe the initial inquiry has been addressed. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.