Honored Contributor II
10-03-2017 03:00 PM
I everyone,I have some issues when implementing Transceiver on an Arria10 FPGA Here is a recap : Attila board (RXCA10X115PF40-IDK00A) with Arria10 GX Device IP instanciate with QSys :
- fPLL generating a 125MHz clock with the 100MHz from a SI53306 on board oscillator
- ATXPLL generating a 625MHz clock (for TX serialization) with the 125MHz from fPLL
- Transceiver Native PHY with one RX/TX channel, PCS direct, 1250Mbps datarate, clock division factor of 1, CDR clock fed with the 125MHz clock
- 50MHz NIOS II (clock from IOPLL)
- 3 PIO IP named "control", "data_in", "data_out"
- parrallel data are registered with NIOS II using the PIO "data_out" (only one time, to avoid clock timing issues)
- data are serialized with TX part of Transceiver, then go on FPGA pin AJ36/AJ37
- We create a physical loopback on a 400 point FMC connector with a second card
- data arrive on FPGA pin AF30/AF31 and then deserialized with RX part of transceiver
- a change on the value of PIO "control" create a pulse signal (clock 50MHz) which is converted into an other pulse signal (clock rx_clkout from transceiver)
- parrallel data are registered on the second pulse signal on PIO "data_in"