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5882 Discussions

Transceiver PHY IP Core questions

Altera_Forum
Honored Contributor II
838 Views

I everyone, 

I have some issues when implementing Transceiver on an Arria10 FPGA 

Here is a recap : 

Attila board (RXCA10X115PF40-IDK00A) with Arria10 GX Device 

IP instanciate with QSys : 

  • fPLL generating a 125MHz clock with the 100MHz from a SI53306 on board oscillator 

  • ATXPLL generating a 625MHz clock (for TX serialization) with the 125MHz from fPLL 

  • Transceiver Native PHY with one RX/TX channel, PCS direct, 1250Mbps datarate, clock division factor of 1, CDR clock fed with the 125MHz clock 

  • 50MHz NIOS II (clock from IOPLL) 

  • 3 PIO IP named "control", "data_in", "data_out" 

 

 

Principle 

  • parrallel data are registered with NIOS II using the PIO "data_out" (only one time, to avoid clock timing issues) 

  • data are serialized with TX part of Transceiver, then go on FPGA pin AJ36/AJ37 

  • We create a physical loopback on a 400 point FMC connector with a second card 

  • data arrive on FPGA pin AF30/AF31 and then deserialized with RX part of transceiver 

  • a change on the value of PIO "control" create a pulse signal (clock 50MHz) which is converted into an other pulse signal (clock rx_clkout from transceiver) 

  • parrallel data are registered on the second pulse signal on PIO "data_in" 

 

 

Here is the problem : 

The transmission part seems good, we see the data serialized at a good frequency 

But on the receiver side, the PMA seems not locked (signal lockedtodata and lockedtoref at 0, and rx_pma_clock frequency is not good), moreover the data on PIO "data_in" are not what we want. 

We are on this problem since a long time and did not see where is the bug, is anyone has tried this kind of configuration ? Is the frequency too low for the transceiver PHY ? 

 

Best regards
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