Transmit error of TSE without internal FIFO

FPGA Intellectual Property

PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP

Transmit error of TSE without internal FIFO

954 Views

Hi,

I've been trying to configure Altera's TSE in FIFO less mode using Altera's TSE example design. In this example I've changed the properties of TSE to be without internal FIFO. Now to make it work, I've added DC FIFO between TSE tx/rx ports and SGDMA blocks. I'm able to receive packets, but I'm unable to transmit them. To be precise, they seem to be transmitted (LED blinks), yet they are not visible on the receiving site. The packet seems to arrive, since there is increased frame counter for the receiving NIC, yet it also increases RX error counter, strangely, by two. This somehow indicates something is wrong with adding FEC (CRC) by MAC function.

Does anyone can help with this, since I'm stack at this for some time now.

I've attached the project archive for your convenience.

Many thanks

Zdenek

Link Copied

0 Replies

Community support is provided during standard business hours (Monday to Friday 7AM - 5PM PST). Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.