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Transmit error of TSE without internal FIFO

Altera_Forum
Honored Contributor II
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Hi, 

I've been trying to configure Altera's TSE in FIFO less mode using Altera's TSE example design. In this example I've changed the properties of TSE to be without internal FIFO. Now to make it work, I've added DC FIFO between TSE tx/rx ports and SGDMA blocks. I'm able to receive packets, but I'm unable to transmit them. To be precise, they seem to be transmitted (LED blinks), yet they are not visible on the receiving site. The packet seems to arrive, since there is increased frame counter for the receiving NIC, yet it also increases RX error counter, strangely, by two. This somehow indicates something is wrong with adding FEC (CRC) by MAC function. 

 

Does anyone can help with this, since I'm stack at this for some time now. 

 

I've attached the project archive for your convenience. 

 

Many thanks 

Zdenek
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