Tri-Speed Ethernet IP - Link Status up

[SKon1]

Hello,

I'm using the Tri-Speed Ethernet IP on an Arria V FPGA.

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_ethernet.pdf 

The IP is configured as "PCS Only".

After power-up I expect the Status Register ( address 0x01 - page 94 in the user guide ) to show the value 0x89.

However, what I see is 0x8D - which means the link is up.

And it happens after power-up before I enable anything.

Why does this happen ?

[SengKok_L_Intel]

Hi Sir,

Yes, you have to initialize the PCS after power-up. What are the status LED signals (e.g Led_link)? Are you consistently read out 0x8D even the Led_link signal is not asserted?

Regards -SK

[SKon1]

The Led Link status isn't connected to an actual LED so I'll have to check it using Signal Tap - I'll update on this.

What I can say now is that I consistently read out 0x8D after power-up WITHOUT INITIALIZING the IP. I don't do anything - just power up and I'm able to read 0x8D.

I was expecting 0x89 up to the point I initialize the IP over using the Avalon Bus...

[SengKok_L_Intel]

Hi,

There is a Link Synchronization block in the PCS, this block is to ensure CDR is stable and word alignment. Ethernet can achieve link if received 3 common characters (K28.5/D16.2).

To confirm if this is not the register at address 0x01 reporting the wrong info. It will be a great help if you can confirm the led link status signal. Besides, please unplug any connector to the TSE IP ethernet port to confirm if this can read out 0x89.

Regards -SK

[SKon1]

I checked it with signal tap - the led_an signal is high.

There's no connector to unplug - the FPGA is connected to the external device on a single board (via SGMII PCB traces - not over an Ethernet CAT cable).

[SengKok_L_Intel]

Are you saying led_an is high or led_link? If without any initialization, I don't think the led_an will be asserted.

Could you also read the value from "if_mode" register after reset/power on, this value should be 0?

Regards -SK

[SKon1]

After startup led_link is up led_an is down.

if_mode is indeed 0.

[SengKok_L_Intel]

Thank you for the clarification.

The register at address 1 is reporting the correct info since the led_link is up. The led_link is up probably is because of the TSE's transceiver is connecting to the onboard PCB traces, and the CDR can be locked after power on if another end of the transceiver is also active.

Regards -SK

[SKon1]

So I don't have to initialize the IP in order for the IP to report "Link Status" up ?

This is counter intuitive...it seems logical (at list to me) that "Linking" would be a bidirectional event.

From what your're saying - in order for the IP to report the link is up it's enough only for the far end device to transmit ?

[SengKok_L_Intel]

Hi

Yes, the link sync is up if it can receive 3 common characters. From the simulation, I can also observe the led_link is asserted before the register initialization.

Regards -SK

[SKon1]

So no register configurations are required to get the link up ?

[SengKok_L_Intel]

Yes, the link sync can achieve if without register configuration.

Regards -SK

[SKon1]

Thanks,

I'm having a strange problem with this core in loopback mode.

Please help:

https://forums.intel.com/s/question/0D50P00004h5V13SAE/tse-pcs-only-internal-loopback-problem?language=en_US

[SengKok_L_Intel]

Hi,

Yes, I can help to look at that forum and set this one to close-pending. After 15 days, this thread will be transitioned to community support. The community users will be able to help you with your follow-up questions.

Regards -SK