Hi,Has anyone tried using Altera's IP-SDI with HD-SDI on smaller package like the C4-GX15 or GX22 ? Anyone knows why Altera do not want to support HD-SDI in a device where the transceiver is capable of handling twice the required speed. Then What's the point of even putting transceiver into these chips? Puzzled, Paul
Well, I do not think so. There must be a MPLL that is "absorbed" into the IP-core block for it to work. The same fabric with similar speed, as specified in the datasheet for all the different die size. The only difference is the lead-frame, which lead to slightly lower speed limit on its I/O pin. To add to the gist, the whole chip does nothing but just a transceiver and IP-core. Utilization is less than 5% !!Asking FAE, will be difficult, as some are 'hiding' behind the published user's guide and try to give me a 'textbook' answer.
More like marketing and resources now. It is badly maintained, with too much inflexibility around a so-call FPGA. It tells you, can do this and that in the datasheet and handbook, but Quartus will not allow it.