FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
6355 Discussions

Triple SDI RX - Clocked Video Input Interface

Altera_Forum
Honored Contributor II
1,916 Views

Hello, I am trying to convert the output of Triple SDI RX to the Avalon Video stream using Clocked Video Input. However, I am not able to obtain any signals at the output of Clocked Video Input. The output of SDI RX is HD-SDI and it seems OK when observing with Signal Tap(1080p60). At this point, I am not sure about the connection between SDI RX and Clocked Video Input. I am using Clocked Video Input with Embedded Sync with SDI 1080p60 arrangement. I connected Clocked_Video_Intput_vid_data(19:0) to SDI_rx_data(19:0) and Clocked_Video_Input_vid_clk to SDI_rx_clk. What about Video_Clocked_Input_vid_datavalid and Video_Clocked_Input_vid_locked signals? Do I have to connect connect them data_valid signal of SDI RX? Thank you,

0 Kudos
3 Replies
Altera_Forum
Honored Contributor II
346 Views

Were you able to fix your issue? I have the same problem. How did you make your connections between the SDI Rx core and VIP clocked video input block?

0 Kudos
Altera_Forum
Honored Contributor II
346 Views

I partly solved the problem by making the connections below (using embedded sync): 

 

rx_clk --> vid_clk 

rx_data(19:0) --> vid_data 

rx_data_valid_out(0) --> vid_datavalid 

rx_data_valid_out(0) --> vid_locked 

 

I obtained video correctly, however, at this time I have an overflow issue for Video Clocked Input for every about 2 minutes. I analyzed downstream functions, but did not found anything that causes overflow.
0 Kudos
Altera_Forum
Honored Contributor II
346 Views

For vid_locked input, try connecting to trs_locked signal from the SDI Rx core instead of the datavalid signal.

0 Kudos
Reply