Triple Speed Ethernet IP - 1000BASE-X/SGMII PCS only - word alignment included?

[AThom47]

When implementing the Triple Speed Ethernet IP with the core variation "1000BASE-X/SGMII PCS only" WITHOUT built in transceiver (Transceiver type selection is set to "None") does the IP do word alignment or not?

The user guide (https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_ethernet.pdf) on page 61 "4.2.3.1. Comma Detection" states:

"The comma detection function searches for the 10-bit encoded comma character, K28.1/K28.5/K28.7, in consecutive samples received from PMA devices. When the K28.1/K28.5/K28.7 comma code group is detected, the PCS function realigns the data stream on a valid 10-bit character boundary. A standard 8b/10b decoder can subsequently decodes the aligned stream. The comma detection function restarts the search for a valid comma character if the receive synchronization state machine loses the link synchronization."

It sounds like bit slipping could be included but it could also be interpreted such that the IP is only looking for the comma characters in the 10 bit words it gets presented with but NOT doing bit slips to get to the correct 10 bit word alignment. Or it could mean that it is doing word alignment but only when the transceiver is included with the IP (Transceiver type is set to LVDS I/O or GXB). It is not clear to me.

Thanks!

[Nathan_R_Intel]

Hie,

Currently the word alignment is done by the transceiver. Hence, word alignment is only done if the transceiver is included.

Regards,

Nathan

[AThom47 · Accepted solution]

I have tried this in hardware since I asked and the answer from Nathan above is incorrect. The 1000BASE-X/SGMII PCS only version of the tripe speed ethernet IP actually does word alignment internally. Word alignment on the tbi interface out of the rx serdes is NOT needed.

Also, the tse user guide actually states that in the port description:

"tbi_rx_d[9:0] - TBI receive data. This bus carries the data from the external SERDES. Synchronize the bus with tbi_rx_clk. The data can be arbitrary aligned."

Just wanted to update if anyone else is ever wondering about this.

[Nathan_R_Intel]

Hie,

Based on your last response, I re-investigated the Triple Speed Ethernet (TSE) IP in 1000Base-x/SGMIII PCS configuration.

You are correct, currently the incoming TBI receive signal does not require the data to be aligned. My findings is aligned with your investigation.

My apologies, for the previous incorrect description. I configured the TSE IP with 1000Base-X/SGMII PCS only and selected the Transceiver and noticed the hard word aligner block was selected. Hence, I made my conclusion from there that word alignment is only done if transceiver is selected.

Hence, further investigation showed that 8B/10B decoder on the SGMII PCS has additional logic to determine the correct word boundary.

My apologies again for the technical mistake.

Regards,

Nathan

[AThom47]

Thanks Nathan for the update and explanation. I am glad it makes all sense and we are on the same page.

[Nathan_R_Intel]

Yes sure, thanks for discovering my technical mistake