I've begun work with the Triple-Speed Ethernet (TSE) IP in order to simulate packet receiving and sending. I have an external packet generator alongside the main and testbench verilog files. I used Platform Designer (Qsys) to aid in design.
In simulation, my testbench shows proper behavior of the packet_sender, but my rx and tx signals (related to the IP core) remain unchanged. They result in x's if I don't initially give values to them. Proper behavior would have the data from the packet sender sent to the tx bus and then finally from the tx bus to the rx bus.
Below I have attached my code, Platform Designer diagram and outputting waveform.
I'd appreciate any feedback & thanks in advance!
From your simulation, did you initialize the TSE IP register? Please refer to chapter 5.3 in the following link. Besides, I would suggest you generate the design example to run the simulation, you can refer to chapter 9 for the simulation testbench:
Hello & thank you for your response Seng,
Chapter 5.3 states "When using the Triple-Speed Ethernet IP core with an external interface, you must understand the requirements and initialize the registers."
- Because I am doing internal testing and simulation, do I still need to initialize the registers?
- If so, would that be simply adding these lines into the testbench?
- How are these lines formatted? Example: "Wait Command_config Register = 0x00802220" I don't believe this is a valid assignment in Verilog.
- Yes, this still needs to initialize the register.
- It requires to configure the register via the AVMM interface. You may refer to the example design for the simulation.
- That is correct. You can refer to figure 42 for the detail of the command_config register.