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Hello,
I try to run the Triple Speed Ethernet MAC IP with IEEE 1588 support on a Cyclone V GX device.
My configuration is:
- Core Variation: "10/100/1000-Mbps MAC with 1000BASE-X/SGMII PCS"
- Uncheck "Use Internal FIFO"
- Transceiver Type: GXB
- Enable Timestamping
Problem: I need to check "Enable SGMII bridge" to be able to check "Enable Timestamping"
Why is the SGMII bridge mandatory for IEEE 1588?
On my board, the FPGA will be connected to an SGMII PHY with only 1000Mbps data rate. 10Mbps and 100 Mbps won't be used since thys PHY is connected to an onboard GbE switch.
Thanks for confirmation
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Additional information: All is done using the latest Quartus Prime 23.1std
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Hello,
Apologies for the delayed response.
The Triple-Speed Ethernet Intel FPGA IP supports the IEEE 1588v2 feature only in the following configurations:
• 10/100/1000-Mbps MAC with 1000BASE-X/SGMII PCS and embedded serial PMA without FIFO buffer in full-duplex mode
• 10/100/1000-Mbps MAC with 1000BASE-X/SGMII PCS and embedded LVDS I/O without FIFO buffer in full-duplex mode
• 10/100/1000-Mbps MAC without FIFO buffer in full-duplex mode
• 10/100/1000-Mbps Ethernet MAC with 1000BASE-X/SGMII 2XTBI PCS without FIFO buffer in full-duplex mode
So, SGMII is required for IEEE protocol.
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Hello,
We didn't hear from you since last update. If you have a new question, feel free to open a new thread to get the support from Altera experts.
Otherwise, the community users will continue to help you on this thread.
Thank you.
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Hello,
I'm not happy with your answer since it doesn't fit my question.
In the documentation it is very clear I've got to use the listed configurations, but the "10/100/1000-Mbps MAC with 1000BASE-X/SGMII PCS" choice means that you can use either 1000BASE-X (Single Speed PCS at 1000 Mbps) or SGMII (Multi Speed PCB with 10/100/1000 Mbps). I would like to use 1000BASE-X but for that I need to disable the SGMII bridge PCS option, which I can't do when I try to configure my IP. Why?
Best Regards,
Christophe

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