Triple Speed Ethernet MAC core usage

[Altera_Forum]

Hello, 

I am new to ethernet interfacing so finding it very difficult to use TSE MAC core in my design. I have generated the TSE MAC core from mega wizard for 10/100/1000 MBPS ethernet MAC. Now I have got one VHDL file for this TSE MAC core component but I am not able to use it because I don't have any reference design or any application note. I don't know how to use these rx and tx fifo signals, control signals, clock and reset signals and MDIO signals and RGMII interface signals. I am using Cyclone 3 development board and there I checked for connections between FPGA and PHY chip, it is RGMII only. I don't want to use Nios II processor now to communicate with other ethernet node. Please help me in learning and achieving my task. If any reference deign in VHDL language or any step by step guide is there then please share with me.  Thanks in advance, Shruti

[Altera_Forum]

Please explain better. 

You mean you don't want to use with Nios II? So what way is it intended to work? Since you use a Cyclone dev board I believe you don't have another host processor to connect tse to.

[Altera_Forum]

Hi Cris72, 

Is it necessary to use NIOS processor for using TSE MAC core? Actually my plan was to first check for TSE MAC core whether it is working fine or not then I will use Nios processor to implement some TCP/IP or UDP/IP stack. For this, I planned to send some ethernet packets from ethernet packet generator tool to TSE MAC core and see the clocks and receive data on signal tap. then later i will collect the data in some buffer and retransmit them to my PC and check transmit data on signal tap and verify with ethreal tool. is there any issue with this procedure? do i need to configure the TSE MAC core and PHY chip first to start communication through my VHDL design?  Thanks

[Altera_Forum]

What you are planning to do is feasible, but I really don't know how to do it. 

You need to pre-configure all tse registers or have some device which make this for you after fpga design has loaded and this is what I do with Nios. PHY is a lesser problem since you can use the standard configuration or you can use configuration strap pins which are usually available. You need better support than what I can give you.  Cris

[Altera_Forum]

Thanks Cris. 

So can you please tell me, how have you configured the TSE MAC core and PHY through Nios or some reference design which provides this information.  Can somebody else help me out in this matter.  Thanks

[Altera_Forum]

Hi Shruti, 

Take a look to this thread dated only a few days ago: http://www.alteraforum.com/forum/showthread.php?t=24363 Here I posted a sample you can import in sopc builder.  You find further information and reference designs on Altera website http://www.altera.com/support/examples/nios2/exm-nios2.html  Regards Cris

[Altera_Forum]

Thank you Cris. I have downloaded the files and will look into it shortly.  

But is there someone who have used this TSE MAC core without Nios processor?  and configured the registers of MAC and PHY to communicate with PC?  Is there any reference design available to do the above activity via VHDL coding? If so then please share with me..:)  Thanks in advance, Shruti

[Altera_Forum]

No response... 

No one in this forum have ever tried to use TSE MAC without Nios?  Please reply soon, thanks.

[Altera_Forum]

same problem...i am trying to get it done without nios, but i dont know how to deal with the registers...

[Altera_Forum]

I think you could try to config it though "writedata[31..0] and address[7..0] port".I have configed it,and MAC ran perfectly. 

However,i can't do it in niosii , whitout uc/osii.Could someone give me a sample example in niosii?

[Altera_Forum]

--- Quote Start ---  Hello, I am new to ethernet interfacing so finding it very difficult to use TSE MAC core in my design. I have generated the TSE MAC core from mega wizard for 10/100/1000 MBPS ethernet MAC. Now I have got one VHDL file for this TSE MAC core component but I am not able to use it because I don't have any reference design or any application note. I don't know how to use these rx and tx fifo signals, control signals, clock and reset signals and MDIO signals and RGMII interface signals. I am using Cyclone 3 development board and there I checked for connections between FPGA and PHY chip, it is RGMII only. I don't want to use Nios II processor now to communicate with other ethernet node. Please help me in learning and achieving my task. If any reference deign in VHDL language or any step by step guide is there then please share with me.  Thanks in advance, Shruti  --- Quote End ---   Similarly, I am doing such a job recently. I seems that you should follow the megacore function userguide which would teach you to use these rx and tx fifo signals, control signals, clock and reset signals etc. It supports RGMII. My work is using tse's PCS and PMA function, that is 1000BASE-X/SGMII PCS function with an embedded PMA. But I encounted a problem. It seems that the link between SFP and FPGA has not been established.