I am trying to constrain the MDIO port using set_input_delay for the Altera TSE IP core. I am a bit confused because the PHY chip & IEEE spec show a max 300ns clock to out relative to the MDC clock. However the TSE appears to capture the MDIO input using the avalon QSYS input to the module which is much higher rate than the MDC frequency. It doesn't appear to be put into a synchronizer based on the post synthesis netlist viewer. I am confused how to properly constrain this input given this.
Would like to confirm are you from US MAG account ?
There is special compliance policy in supporting MAG account. I would recommend for you to reach out to Intel FAE/dFAE for special arrangement on MAG account support.
Below is Intel policy regarding MAG account support :
Due to US and other countries’ export regulations, any questions, technical support, services, feedback, guidance, optimization, training, assistance, or other work performed by Intel that are directed toward the incorporation and/or implementation of Intel’s product in a military, defense intelligence, nuclear/biochemical or space item may result in a defense service or the transfer of technical data and require authorization from the US or other applicable governments.
For these reasons, Intel is unable to support any such requests in this forum.
What is a MAG account?
I purchased licenses thru Digikey . Thru the Intel license webpage I have tried 2x to request premium support as opposed to the forum and both times it tells me I should here back in ~24 hrs and nobody evert responds to me. I have been trying to find out how to get access to an FAE for questions like this but have been unable to so far. If you can assist in how to get a contact it would be greatly appreciated.
MAG stand for "military aerospace government" account.
Below is the list of dFAE for USA. You can try to contact them.
I find out more about MAG account support requirement. Apparently we still able to support MAG account customer as long as it doesn't involve design info exchange and limited to more FPGA general usage enquiry.
So, I guess it's fine to answer your TSE IP usage enquiry questions.
Intel TSE IP has clock divider setting called "host clock divisor" to lower down the MDIO bus operating frequency.
You can refer to below TSE user guide doc table 19 (page 27)
Intel recommends that the division factor is defined such that the MDC frequency does not exceed 2.5 MHz. (< 3.33MHz or max 300ns spec requirement)
So, as long as you configure the MDC clk to be 2.5MHz then it's pretty safe and doesn't required additional timing constraint.