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Altera_Forum
Honored Contributor I
821 Views

Triple speed ethernet IP core don't receive the RGMII data?

I use the triple speed ethernet IP core with an external PHY Device, the first picture is shown as my test block diagram . Transmiting part works normally, however, There is no data on the avalon-ST side while the RGMII receive interface is transmitting data. that is , some data can be captured at point "a" by using signalTap II, but nothing comes out of MAC IP 2 and the receive counters of IP core is zero.  

Why has this happened? ? what should i do now? 

 

Furthermore, I made an experiment with block diagram 2. The receive count value of MAC1 equals the transmit count value of MAC2. I can see that the link LED is light and the activity LED is blinking. This messages indicate the ping request packets(that is ARP request packets) is transmited correctly. but no response at the side of PC1. Take the previous experiment into consideration, I suspect these packets don't received by MAC layer of PC2.  

 

What caused this phenomenon? what should i do next?:confused: 

https://www.alteraforum.com/forum/attachment.php?attachmentid=8065  

https://www.alteraforum.com/forum/attachment.php?attachmentid=8066
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11 Replies
Altera_Forum
Honored Contributor I
45 Views

What kind of packets do you generate? They could be malformed. Did you configure the MAC addresses on both sides? By default, if the TSE isn't configured in promiscuous modes it will only receive broadcast packets and those that have it's MAC as destination address. The other packets will be thrown away.

Altera_Forum
Honored Contributor I
45 Views

Firstly, the generated packets are repeated ARP request according with its standard. 

Secondly, promiscuous mode is enabled in my design, and all frames should be received without address filtering. so I didn't configure the MAC address.
Altera_Forum
Honored Contributor I
45 Views

Do you perhaps have a pin assignment or board defect with your 2nd MAC and 2nd PHY ?  

 

Assuming that your 2nd diagram that is incorrect, and that you have correctly implemented bidirectional buffer, I think your experiment should have worked. You can investigate further by using something like TCPDUMP/WireShark on each PC to confirm that PC2 is actually receiving anything (and that it matches what PC1 transmitted). But overall from your problem description, it sounds like the packet is getting corrupted/dropped on the 2nd RGMII or PHY. If I'm not mistaken, it sounds like you have never seen anything operate correctly on the 2nd port. 

 

You can further dig into it with SignalTap (tap both sides of both MAC), but I think that would be possibly more time consuming to discover you have an underlying hardware problem. And if you are software inclined, I would suggest implementing the standard NIOS ethernet design and "Simple Socket Server" as a debug tool on just the 2nd MAC/PHY until it is working correctly.
Altera_Forum
Honored Contributor I
45 Views

 

--- Quote Start ---  

Do you perhaps have a pin assignment or board defect with your 2nd MAC and 2nd PHY ?  

 

Assuming that your 2nd diagram that is incorrect, and that you have correctly implemented bidirectional buffer, I think your experiment should have worked. You can investigate further by using something like TCPDUMP/WireShark on each PC to confirm that PC2 is actually receiving anything (and that it matches what PC1 transmitted). But overall from your problem description, it sounds like the packet is getting corrupted/dropped on the 2nd RGMII or PHY. If I'm not mistaken, it sounds like you have never seen anything operate correctly on the 2nd port. 

 

You can further dig into it with SignalTap (tap both sides of both MAC), but I think that would be possibly more time consuming to discover you have an underlying hardware problem. And if you are software inclined, I would suggest implementing the standard NIOS ethernet design and "Simple Socket Server" as a debug tool on just the 2nd MAC/PHY until it is working correctly. 

--- Quote End ---  

 

 

Thank you for your reply. 

I am sure pin assignment and board is correct, so the hardware problem should be eliminated. With my 2nd diagram, I really have implemented bidirectional buffer, but it don't still work. There is a limiting condition that PC2 in my experiment must not be install tools like WireShark. The internal loopback function of MAC IP core also be verified successfully, it indicates MAC works normally. 

I guess the packet is getting corrupted on the transmitting path from MAC2 to 2nd port, through the packet can be output of 2nd port, but the receive side don't recognize it. If so, I am confused what caused this corruption, and how to localize the source of the problem?
Altera_Forum
Honored Contributor I
45 Views

 

--- Quote Start ---  

 

I am sure pin assignment and board is correct 

 

--- Quote End ---  

 

 

How did you test this? 

 

i.e. what is different between the configuration where you have confirmed the pin assignments and board is free of defects, and your problematic diagrams in your earlier post?
Altera_Forum
Honored Contributor I
45 Views

 

--- Quote Start ---  

How did you test this? 

 

i.e. what is different between the configuration where you have confirmed the pin assignments and board is free of defects, and your problematic diagrams in your earlier post? 

--- Quote End ---  

 

 

Recently, a similar module had been implemented successfully on the same board. Is there other reasons for the above phenomenon except for some hardware problem ?
Altera_Forum
Honored Contributor I
45 Views

 

--- Quote Start ---  

Recently, a similar module had been implemented successfully on the same board. Is there other reasons for the above phenomenon except for some hardware problem ? 

--- Quote End ---  

 

 

A hardware problem or error on your part connecting the pins is by far the easiest problem. A quick sanity check on that would be to simply assign the 2nd PHY to the 1st MAC and vice versa (i.e. does the problem follow the PHY). If the 2nd PHY starts working and the 1st PHY stops working, you know that you have incorrectly configured/connected the 2nd MAC somehow. 

 

Beyond hardware / pin connection problems, you should review your MAC signal connections, specifically the clocks/resets/streaming interface. It may be worthwhile to skim the Quartus output and look for warnings that are present for one MAC but not the other. 

 

But in your shoes, I would revisit the known-working system and review differences between it and my broken system. 

 

Good luck.
Altera_Forum
Honored Contributor I
45 Views

 

--- Quote Start ---  

A hardware problem or error on your part connecting the pins is by far the easiest problem. A quick sanity check on that would be to simply assign the 2nd PHY to the 1st MAC and vice versa (i.e. does the problem follow the PHY). If the 2nd PHY starts working and the 1st PHY stops working, you know that you have incorrectly configured/connected the 2nd MAC somehow.Beyond hardware / pin connection problems, you should review your MAC signal connections, specifically the clocks/resets/streaming interface. It may be worthwhile to skim the Quartus output and look for warnings that are present for one MAC but not the other.But in your shoes, I would revisit the known-working system and review differences between it and my broken system.Good luck. 

--- Quote End ---  

I test my design according to your advice, and the result shows MAC2 works as the same as MAC. With my 2nd experiment, a net-analysis instrument (smartbits)substitutes for PC2 and detects the receive packets. As a result, the ARP request packets have a CRC error. every packet occupy 78 bytes. the anterior 42 bytes is correct but the rule of latter 36 bytes is unkown. The follow is the receive packet when a ping command sends at side of PC1. I don’t know why CRC error occur?“ FF FF FF FF FF FF B8 CA 3A 8A 83 5A 08 06 00 01 08 00 06 04 00 01 B8 CA 3A 8A 83 5A C0 A8 00 03 00 00 00 00 00 00 C0 A8 00 37 5F 45 64 50 05 23 82 82 CA A2 6E A0 0A 0A 0A 0A 00 00 00 00 C0 A8 00 03 B8 CA 3A 8A 83 5A 00 00 64 98 C8 4A”
Altera_Forum
Honored Contributor I
45 Views

 

--- Quote Start ---  

I test my design according to your advice, and the result shows MAC2 works as the same as MAC. With my 2nd experiment, a net-analysis instrument (smartbits)substitutes for PC2 and detects the receive packets. As a result, the ARP request packets have a CRC error. every packet occupy 78 bytes. the anterior 42 bytes is correct but the rule of latter 36 bytes is unkown. The follow is the receive packet when a ping command sends at side of PC1. I don’t know why CRC error occur?“ FF FF FF FF FF FF B8 CA 3A 8A 83 5A 08 06 00 01 08 00 06 04 00 01 B8 CA 3A 8A 83 5A C0 A8 00 03 00 00 00 00 00 00 C0 A8 00 37 5F 45 64 50 05 23 82 82 CA A2 6E A0 0A 0A 0A 0A 00 00 00 00 C0 A8 00 03 B8 CA 3A 8A 83 5A 00 00 64 98 C8 4A” 

--- Quote End ---  

 

Further test result reveals the 4-byte CRC value is incorrect at sink while other field of packets is received accurately. The weird thing is that only 4-bits of CRC field occur error, moreover, the wrong 4-bits is always a “4” as the pciture shows. I can observe that the CRC value outputed by MAC1 is variable and normal when the CRC function of MAC IP is canceled. I‘m puzzled what caused the regular CRC error? 

https://www.alteraforum.com/forum/attachment.php?attachmentid=8090
Altera_Forum
Honored Contributor I
45 Views

Since your error is 4-bits wide, and since RGMII is a 4-bit wide DDR bus, I think you need to look closer there. 

 

Is the problem something simple like you didn't add the timing constraints for the 2nd port? Double check for timing violations anyway.
Altera_Forum
Honored Contributor I
45 Views

 

--- Quote Start ---  

Since your error is 4-bits wide, and since RGMII is a 4-bit wide DDR bus, I think you need to look closer there. 

 

Is the problem something simple like you didn't add the timing constraints for the 2nd port? Double check for timing violations anyway. 

--- Quote End ---  

 

 

Bit 7 to 4 of CRC-32 field of every received packet becomes a "4" while all other bits is exactly correct. How timing violations could cause such constant error? And, there is still an error after adding some timing constraints to RGMII interface.
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