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Tripple Speed Ethernet Simulation Error :[vlog-2110] Illegal reference to <protected>

Honored Contributor II

Hi guys 


I want to simulate the altera TSE IP core to understand control register read write and working of the core. I have followed the method described in ug_ethernet (https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/ug/ug_ethernet.pdf) section 9-4 & 9-5. 


But unfortunately I am getting these errors 


# vlog -reportprogress 300 -sv /home/vinod/edatools/camera_prj/tse/simulation/submodules/mentor/altera_tse_ph_calculator.sv -work i_tse_mac # ** Warning: (vlog-2644) Conflicting semantics, "-vlog01compat" switch disables SystemVerilog support.# ** Warning: (vlog-2644) Conflicting semantics, "-vlog01compat" switch disables SystemVerilog support.# ** Error: /home/vinod/edatools/camera_prj/tse/simulation/submodules/mentor/altera_tse_ph_calculator.sv(40): (vlog-2110) Illegal reference to <protected> "<protected>".# ** Error: /home/vinod/edatools/camera_prj/tse/simulation/submodules/mentor/altera_tse_ph_calculator.sv(40): in protected region# ** Warning: /home/vinod/edatools/camera_prj/tse/simulation/submodules/mentor/altera_tse_ph_calculator.sv(176): (vlog-2644) Conflicting semantics, "-vlog01compat" switch disables SystemVerilog support.# End time: 20:27:17 on Nov 23,2016, Elapsed time: 0:00:00# Errors: 2, Warnings: 3# ** Error: /home/altera_lite/15.1/modelsim_ase/linuxaloem/vlog failed. 


I checked the altera_tse_ph_calculator.sv file also but that is encrypted. 

I am a newbie to Modelsim and don't know scripting and libraries compilation. 



>> I have installed "Quartus Prime Version 15.1.0 Build 185 10/21/2015 SJ Lite Edition " in Ubuntu 12.04 LTS. 

>> I am developing a UDP packet transmitter using Altera TSE IP core. I have generated the Tripple Speed Ethernet MAC IP core using Qsys and I'm instantiating the "tse.v" top module in my design. 

>> To do proper initial configuration of the TSE MAC IP core I need to read and write its control registers, so for that also I have written all the needed code. 

Now before putting my design on the FPGA I wanted to test it by Simulating via Altera Native Simulation.  


Any help would be greatly appreciated. 

Thank you.
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