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I am having troubles when I try to erase a Micron Flash (MT25QL256) using the Generic Serial Flash Interface in a Cyclone 5 (5CGTFD7C5). This 256Mbit flash part has 512 segments and each segment has 64Kbytes. I can erase certain portions of the flash but not the entire flash.
- Segments 0-31 can be erased
- Segments 32-127 will not erase
- Segments 128-159 can be erased
- Segments 160-255 will not erase
- I don't have data for segments 256 thru 511 but I am assuming they will follow a similar pattern and only the first 32 segments of the region will be erasable.
I know the part is not write protected because I can fill the entire flash using JTAG and a .JIC file.
I am using custom VHDL/Software (not a NIOS) to drive the Avalon busses on the GSFI core. I have narrowed it down to the core. I can watch the custom VHDL issue the proper erase commands, but they don't have any effect for the segments noted above. I have not put an oscilloscope on the QSPI interface to validate if the troublesome commands are making it through the core, nor have I checked to see if they are accurate on the oscilloscope. I only know that the command given to the core to erase segment 31 or 32 or.... has no effect, when I go dump the contents of the flash.
Could there be a licensing issue that "cripples" the core because the licenses are out of date? The tools, when I start them, are saying that "Your subscription has expired" but gives me the option to "Run the Quartus Prime software with existing license". I have searched the log files from the build, but it doesn't show any indication that I am working with an expired license, or working with evaluation versions of any of my cores.
Could there be a tool version issue? I think the core was generated using the 18.0 tools, but i am now using the 20.1 tools?
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Hi,
Thanks for using Intel community forum,
Kindly expect some delay in the reply due to holiday.
Thanks,
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Welcome to INTEL forum. May we know, is this the board that you’re referring to?
https://www.intel.com/content/www/us/en/products/details/fpga/development-kits/cyclone/v-e.html
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Hello,
We can see 2 issues here:
1. The core design was built at 18.0 and programmed at 20.1
2. Please check your license is grant to run at 20.1.
regards,
Farabi
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Those are both good ideas. Here is what I have done and see.
I have now "built" the core in the same version(20.1) of Quartus as I am using to "compile" the code. I don't think this made any differences. I am "compiling" 5 different flavors/functions that go into the same hardware. All flavors have the exact same top levels of code and the exact same flash interfaces (Generic Serial Flash Interface and Remote Update), but they each have a different set of other functions they perform. Of these 5 flavors, one of them behaves correctly. An interesting (hopefully unrelated) observation is that the 4 flavors that don't work are all in the 70% full range and the the 1 flavor that does work is in the 20% full range. In my mind, this was leading me down a timing issue road, but I am baffled by fact the error exhibits itself in exactly the same way for every build (two of the middle address bits get lost somewhere), and it is telling me that everything is constrained and meeting timing.
As for the license, I don't see anything specific related to the Generic Serial Flash Interface IP core in the "License Setup" tool. I see listed products like 0005, 0057, 0001, 0004, Reed-Solomon, Viterbi, Triple-Speed Ethernet, Nios II, ......... and all these have a different date next to them. I see the following dates 2022.12, 2021.12, 2018.10, 2012.08, 2011.07, 2011.08. I am not sure how these dates relate to specific software versions, and I am not sure which license on this list would relate to the Generic Serial Flash Interface. I am assuming that these dates relate to a specific version of software and I don't know what dates apply to Quartus 20.1.
Thanks for continuing to look at this.
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Hello,
From your description, out of 5 flavors , 1 is working. could you please give more information on this? What are the design differences? Maybe we can focus on the working design first, then fix the failed ones.
regards,
Farabi
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Flavor 1 only has
- MII signals (Ethernet Interface) to the Intel Triple Speed Ethernet MAC core.
- Some custom logic that process these ethernet packets and converts them into Avalon bus interfaces and some internal custom bus interfaces
- One Avalon interface connects to the "CSR" interface on the Intel Generic Serial Flash Interface
- One Avalon interface connects to the "MEM" interface on the Intel Generic Serial Flash Interface
- the custom bus interfaces talks to other internal command/status registers
- An Intel Generic Serial Flash Interface Core
- An Intel Remote Update Core
Here are the summary statistics for Flavor 1
Family : Cyclone V Device : 5CGTFD7C5U19I7 Timing Models : Final Logic utilization (in ALMs) : 4,667 / 56,480 ( 8 % ) Total registers : 7945 Total pins : 114 / 268 ( 43 % ) Total virtual pins : 0 Total block memory bits : 114,688 / 7,024,640 ( 2 % ) Total RAM Blocks : 20 / 686 ( 3 % ) Total DSP Blocks : 0 / 156 ( 0 % ) Total HSSI RX PCSs : 0 / 6 ( 0 % ) Total HSSI PMA RX Deserializers : 0 / 6 ( 0 % ) Total HSSI TX PCSs : 0 / 6 ( 0 % ) Total HSSI PMA TX Serializers : 0 / 6 ( 0 % ) Total PLLs : 1 / 13 ( 8 % ) Total DLLs : 0 / 4 ( 0 % )
Flavors 2,3,4,5 have
- the exact same things listed in flavor 1 plus the following
- Various processing functions
- Intel Cores (Reed Solomon Decoder, Viterbi Decoder, FFT)
- Third Party Video Encoder Core
- Custom Radio signal processing blocks (Filters, FEC Decoders, Protocol Decoders)
Here are the Statistics for flavors 2 and 3 (4 and 5 are similar)
Family : Cyclone V Device : 5CGTFD7C5U19I7 Timing Models : Final Logic utilization (in ALMs) : 38,276 / 56,480 ( 68 % ) Total registers : 60421 Total pins : 114 / 268 ( 43 % ) Total virtual pins : 0 Total block memory bits : 1,426,677 / 7,024,640 ( 20 % ) Total RAM Blocks : 262 / 686 ( 38 % ) Total DSP Blocks : 156 / 156 ( 100 % ) Total HSSI RX PCSs : 0 / 6 ( 0 % ) Total HSSI PMA RX Deserializers : 0 / 6 ( 0 % ) Total HSSI TX PCSs : 0 / 6 ( 0 % ) Total HSSI PMA TX Serializers : 0 / 6 ( 0 % ) Total PLLs : 1 / 13 ( 8 % ) Total DLLs : 0 / 4 ( 0 % )
Family : Cyclone V Device : 5CGTFD7C5U19I7 Timing Models : Final Logic utilization (in ALMs) : 39,758 / 56,480 ( 70 % ) Total registers : 73475 Total pins : 114 / 268 ( 43 % ) Total virtual pins : 0 Total block memory bits : 2,059,980 / 7,024,640 ( 29 % ) Total RAM Blocks : 327 / 686 ( 48 % ) Total DSP Blocks : 136 / 156 ( 87 % ) Total HSSI RX PCSs : 0 / 6 ( 0 % ) Total HSSI PMA RX Deserializers : 0 / 6 ( 0 % ) Total HSSI TX PCSs : 0 / 6 ( 0 % ) Total HSSI PMA TX Serializers : 0 / 6 ( 0 % ) Total PLLs : 1 / 13 ( 8 % ) Total DLLs : 0 / 4 ( 0 % )
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Hello,
Thanks for the information. I will send you email to request your license file.
regards,
Farabi
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Hello Mark,
We are checking the license and will update in email.
regards,
Farabi
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Hello Mark,
Could you please run the design compilation as below:
https://www.intel.com/content/www/us/en/support/programmable/articles/000080459.html?wapkw=6AF7_BCE1
this is to check which license has problem.
Regards,
Farabi
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Hello,
We do not receive any response from you to the previous question/reply/answer that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.
regards,
Farabi
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The above link says to look in the ......asm.rpt. It is actually the .....map.rpt that shows what IP is being used and what the license status is. Here is the License section from one of my builds where the intel_generic_serial_flash_interface doesn't work correctly. But I don't see anything that looks concerning.
+------------------------------------------------------------------------------------------------------- ; Analysis & Synthesis IP Cores Summary +--------+----------------------------------------------+---------+--------------+--------------+------- ; Vendor ; IP Core Name ; Version ; Release Date ; License Type ; Entity +--------+----------------------------------------------+---------+--------------+--------------+------- ; Altera ; altera_pll ; 20.1 ; N/A ; N/A ; |top_u ; Altera ; Triple Speed Ethernet ; 12.1 ; N/A ; N/A ; |top_u ; Altera ; Triple Speed Ethernet ; N/A ; Nov 2012 ; Licensed ; |top_u ; Altera ; Triple Speed Ethernet ; N/A ; Nov 2012 ; Licensed ; |top_u ; Altera ; Triple Speed Ethernet ; N/A ; Nov 2012 ; Licensed ; |top_u ; Altera ; Triple Speed Ethernet ; N/A ; Nov 2012 ; Licensed ; |top_u ; Altera ; Triple Speed Ethernet ; N/A ; Nov 2012 ; Licensed ; |top_u ; Altera ; Triple Speed Ethernet ; N/A ; Nov 2012 ; Licensed ; |top_u ; Altera ; Triple Speed Ethernet ; N/A ; Nov 2012 ; Licensed ; |top_u ; Altera ; Triple Speed Ethernet ; N/A ; Nov 2012 ; Licensed ; |top_u ; Altera ; Triple Speed Ethernet ; N/A ; Nov 2012 ; Licensed ; |top_u ; Altera ; Triple Speed Ethernet ; N/A ; Nov 2012 ; Licensed ; |top_u ; Altera ; Triple Speed Ethernet ; N/A ; Nov 2012 ; Licensed ; |top_u ; Altera ; Triple Speed Ethernet ; N/A ; Nov 2012 ; Licensed ; |top_u ; Altera ; Triple Speed Ethernet ; N/A ; Nov 2012 ; Licensed ; |top_u ; Altera ; Triple Speed Ethernet ; N/A ; Nov 2012 ; Licensed ; |top_u ; Altera ; Triple Speed Ethernet ; N/A ; Nov 2012 ; Licensed ; |top_u ; Altera ; Triple Speed Ethernet ; N/A ; Nov 2012 ; Licensed ; |top_u ; Altera ; Triple Speed Ethernet ; N/A ; Nov 2012 ; Licensed ; |top_u ; Altera ; Triple Speed Ethernet ; N/A ; Nov 2012 ; Licensed ; |top_u ; Altera ; Triple Speed Ethernet ; N/A ; Nov 2012 ; Licensed ; |top_u ; Altera ; Triple Speed Ethernet ; N/A ; Nov 2012 ; Licensed ; |top_u ; Altera ; Triple Speed Ethernet ; N/A ; Nov 2012 ; Licensed ; |top_u ; Altera ; Triple Speed Ethernet ; N/A ; Nov 2012 ; Licensed ; |top_u ; Altera ; Triple Speed Ethernet ; N/A ; Nov 2012 ; Licensed ; |top_u ; Altera ; Triple Speed Ethernet ; N/A ; Nov 2012 ; Licensed ; |top_u ; Altera ; Triple Speed Ethernet ; N/A ; Nov 2012 ; Licensed ; |top_u ; Altera ; Triple Speed Ethernet ; N/A ; Nov 2012 ; Licensed ; |top_u ; Altera ; Triple Speed Ethernet ; N/A ; Nov 2012 ; Licensed ; |top_u ; Altera ; Triple Speed Ethernet ; N/A ; Nov 2012 ; Licensed ; |top_u ; Altera ; Triple Speed Ethernet ; N/A ; Nov 2012 ; Licensed ; |top_u ; Altera ; Triple Speed Ethernet ; N/A ; Nov 2012 ; Licensed ; |top_u ; Altera ; Triple Speed Ethernet ; N/A ; Nov 2012 ; Licensed ; |top_u ; Altera ; Triple Speed Ethernet ; N/A ; Nov 2012 ; Licensed ; |top_u ; Altera ; Triple Speed Ethernet ; N/A ; Nov 2012 ; Licensed ; |top_u ; Altera ; Triple Speed Ethernet ; N/A ; Nov 2012 ; Licensed ; |top_u ; Altera ; Triple Speed Ethernet ; N/A ; Nov 2012 ; Licensed ; |top_u ; Altera ; Triple Speed Ethernet ; N/A ; Nov 2012 ; Licensed ; |top_u ; Altera ; Triple Speed Ethernet ; N/A ; Nov 2012 ; Licensed ; |top_u ; Altera ; Triple Speed Ethernet ; N/A ; Nov 2012 ; Licensed ; |top_u ; Altera ; Triple Speed Ethernet ; N/A ; Nov 2012 ; Licensed ; |top_u ; Altera ; Triple Speed Ethernet ; N/A ; Nov 2012 ; Licensed ; |top_u ; Altera ; Triple Speed Ethernet ; N/A ; Nov 2012 ; Licensed ; |top_u ; Altera ; Triple Speed Ethernet ; N/A ; Nov 2012 ; Licensed ; |top_u ; Altera ; Triple Speed Ethernet ; N/A ; Nov 2012 ; Licensed ; |top_u ; Altera ; Triple Speed Ethernet ; N/A ; Nov 2012 ; Licensed ; |top_u ; Altera ; Triple Speed Ethernet ; N/A ; Nov 2012 ; Licensed ; |top_u ; Altera ; Triple Speed Ethernet ; N/A ; Nov 2012 ; Licensed ; |top_u ; Altera ; Triple Speed Ethernet ; N/A ; Nov 2012 ; Licensed ; |top_u ; Altera ; Triple Speed Ethernet ; N/A ; Nov 2012 ; Licensed ; |top_u ; Altera ; Triple Speed Ethernet ; N/A ; Nov 2012 ; Licensed ; |top_u ; Altera ; Triple Speed Ethernet ; N/A ; Nov 2012 ; Licensed ; |top_u ; Altera ; Triple Speed Ethernet ; N/A ; Nov 2012 ; Licensed ; |top_u ; Altera ; Triple Speed Ethernet ; N/A ; Nov 2012 ; Licensed ; |top_u ; Altera ; Triple Speed Ethernet ; N/A ; Nov 2012 ; Licensed ; |top_u ; Altera ; Triple Speed Ethernet ; N/A ; Nov 2012 ; Licensed ; |top_u ; Altera ; Triple Speed Ethernet ; N/A ; Nov 2012 ; Licensed ; |top_u ; Altera ; Triple Speed Ethernet ; N/A ; Nov 2012 ; Licensed ; |top_u ; Altera ; Triple Speed Ethernet ; N/A ; Nov 2012 ; Licensed ; |top_u ; Altera ; Triple Speed Ethernet ; N/A ; Nov 2012 ; Licensed ; |top_u ; Altera ; Triple Speed Ethernet ; N/A ; Nov 2012 ; Licensed ; |top_u ; N/A ; intel_generic_serial_flash_interface_top ; 18.0 ; N/A ; N/A ; |top_u ; Altera ; intel_generic_serial_flash_interface_csr ; 18.0 ; N/A ; N/A ; |top_u ; Altera ; altera_merlin_demultiplexer ; 18.0 ; N/A ; N/A ; |top_u ; Altera ; altera_merlin_multiplexer ; 18.0 ; N/A ; N/A ; |top_u ; Altera ; intel_generic_serial_flash_interface_if_ctrl ; 18.0 ; N/A ; N/A ; |top_u ; Altera ; intel_generic_serial_flash_interface_if_ctrl ; 18.0 ; N/A ; N/A ; |top_u ; Altera ; altera_avalon_sc_fifo ; 18.0 ; N/A ; N/A ; |top_u ; Altera ; intel_generic_serial_flash_interface_if_ctrl ; 18.0 ; N/A ; N/A ; |top_u ; Altera ; altera_merlin_multiplexer ; 18.0 ; N/A ; N/A ; |top_u ; Altera ; altera_reset_controller ; 18.0 ; N/A ; N/A ; |top_u ; Altera ; intel_generic_serial_flash_interface_cmd ; 18.0 ; N/A ; N/A ; |top_u ; Altera ; intel_generic_serial_flash_interface_addr ; 18.0 ; N/A ; N/A ; |top_u ; Altera ; intel_generic_serial_flash_interface_xip ; 18.0 ; N/A ; N/A ; |top_u ; Altera ; intel_generic_serial_flash_interface_xip ; 18.0 ; N/A ; N/A ; |top_u ; Altera ; altera_avalon_sc_fifo ; 18.0 ; N/A ; N/A ; |top_u ; N/A ; altera_remote_update ; 20.1 ; N/A ; N/A ; |top_u ; Altera ; altera_remote_update_core ; 20.1 ; N/A ; N/A ; |top_u +--------+----------------------------------------------+---------+--------------+--------------+-------
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