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True Dual Port RAM

Altera_Forum
Honored Contributor II
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hellowhen I use True dual port ram with two inputs and two outputs, if the two inputs insert different values ​​in different memory locations in the two outputs I see only the values ​​for the first entry. the two write enable is activated at the same time for both inputs. What could be the problem?

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Altera_Forum
Honored Contributor II
125 Views

Try using signaltap to look at the actual signals involved.

Altera_Forum
Honored Contributor II
125 Views

thanks 

 

problem solved
Altera_Forum
Honored Contributor II
125 Views

I have another question. In true dual port ram when I have two inputs, two outputs and two addresses if I create a Ram with size of 2048 bits. The size of the RAM will be the first entry for 2048 and 2048 for the second input?

Altera_Forum
Honored Contributor II
125 Views

yes, the ram is common to both ports so the size is the same for both sides if the data port widths are the same. Obviously, if one side A has a Dwidth of 8 and B is 16, then AddrWidth A will be 1 bit larger than AddrWidth B.

Altera_Forum
Honored Contributor II
125 Views

thanks for the reply

Altera_Forum
Honored Contributor II
125 Views

In true dual port Ram signals that are not used, during the synthesis, are not considered or are considered and put such high impedance?

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