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Altera_Forum
Honored Contributor I
743 Views

UART IP Core Interrupt

Hi, 

I am designing a VHDL Avalon Master Module, which is connecting through Qsys to the UART IP Core (address 0x0000 to 0x001f). 

I have read the spec on the Core and the Bus. 

I need a basic Rx Interrupt Flag. This is the RRDY flag set by the IRRDY Bit.  

The problem is the RRDY flag is constantly set to 1. 

I read the data from the rxdata register, which is supposed to clear the flag, but the flag remains high. 

 

Do you have any idea how to clear this flag? or properly read the register? 

 

I am currently reading the register by setting the address to 0x0000 (the rxdata register), select Read = 1 and write = 0. and waiting 2 clock cycles. 

The data read from the rxdata is the data i sent from my computer through an FTDI RS232 Chip. 

 

Any ideas? 

 

Thanks, 

Tom
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4 Replies
Altera_Forum
Honored Contributor I
46 Views

AFAIK if you don't use interrupts (i.e. you don't set IRRDY bit in control register) RRDY status bit indeed behaves that way and it is automatically cleared when you read the rx data. 

If irq is enabled through IIRRDY bit, you must explicitly acknowledge the irq by writing 0 to the status register, otherwise the flag remains asserted.
Altera_Forum
Honored Contributor I
46 Views

Thank you for the response, but it did not work. 

 

I disabled the IRRDY, and read the status bit, and the RRDY flag is a constant 1. 

I enabled the IRRDY, and wrote the status bit to 0, and the RRDY flag is a constant 1. 

 

Any other ideas?
Altera_Forum
Honored Contributor I
46 Views

Then you probably have a timing problem in the core itself or with the Avalon interface. 

Does the data you read from the rx register always match the real rx data?
Altera_Forum
Honored Contributor I
46 Views

The data ia always correct, but I can read the same rx value multiple times. 

I think the problem might be with the readyforread and the dataavailable pins because I dont know where they connrct in the avalon mm
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