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UART IP - input clock

Altera_Forum
Honored Contributor II
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Hello,  

 

I'm using a MAX10 FPGA and I'm trying to generate a UART IP core. During the generation process, after I select the buad rate, stop, parity bits, I get an error "the input clock frequency must be known at generation time". This error makes sense. But how do I set the clock frequency? I've looked though various menus, and did not find anything.  

 

 

Thank you.  

Alin
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Altera_Forum
Honored Contributor II
372 Views

Hi, 

 

Refer below link 

https://www.altera.com/support/support-resources/knowledge-base/ip/2018/error--rs232_0--the-input-clock-frequency-must-be-known-at-gener.html 

 

Let me know if this has helped resolve the issue you are facing or if you need any further assistance. 

 

Best Regards, 

Anand Raj Shankar 

(This message was posted on behalf of Intel Corporation)
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