Unable to enable RX_TNA and TX_ENA bits (Triple-Speed Ethernet IP)

[GDagi1]

Hi all,

I'm working with the Triple-Speed Ethernet IP and currently am in the process of setting up the MAC register space. I am following the order found in 5.3.1 of the Triple-Speed Ethernet User Guide.

I have a state machine, modeled after the generated testbench, which goes through each register and writes the appropriate value. I am able to confirm the written value through Modelsim Simulation and UART output. Everything works as planned until the last step. This is "2f" in the user guide. It states to enable the RX_ENA and TX_ENA bits in the command config register. I have tried doing this but the bits never change to a '1.' They remain 0. I've tried writing just those specific bits high. I also tried writing all 32 bits again to the register, which also didn't work..

I have tested by changing other bits in the register, which worked.

Thanks in advance!

[GDagi1 · Accepted solution]

I believe to have solved the issue. Through prior experience with Intel IP, I had thought to implement a counter to remain in the writing state, as it may take some time for this update to complete. I now see these bits go high. I could not find this explicitly stated within the Triple Speed IP User Guide.

[Deshi_Intel]

HI,

It's good to know you have solved the issue.

One thing to take note is the step 2(E) in TSE user guide doc section 5.3.1.

• You need to wait for SW_RESET bit to clear (change from 1 to 0) before you assert TX_ENA and RX_ENA in step 2(F)

Aright, I am now setting this case to closure.

Thanks.

Regards,

dlim