Unable to generate AXI Streaming Intel FPGA IP for PCIe Example design for F-Tile FPGA Agilex 7 R24C

[h3l1um]

Hello Team,

I am trying to generate an example design for the AXI Streaming Intel FPGA IP for PCI Express IP.
It supports F-Tile PCIe in the design, but when trying to generate the Example design as an Endpoint I am unable to generate one.
Is there any Endpoint Example design for the F-Tile, could you please provide me with the link for the same.|
Quartus Prime Pro 2024.1
Agilex 7 AGFB014R24C2E2V

Thank you,
Best Regards

[RongYuan]

Hi,

From my side, I'm able to generate an example design in Q24.1 Pro.

Please check the Quartus files you downloaded have correct SHA1 checksum.

You can create an empty project based on AGFB014R24C2E2V. In "IP Catalog", find "F-Tile Avalon Streaming Intel FPGA IP for PCI Express" and create an IP. With all default settings, you can click "Generate Example Design" then it should generate one.

Regards,

Rong

[FPGA_Mozart]

Hi RongYuan,

I am still unable to generate the example design. I created a new project with default settings and still unable to generate.

"Please check the Quartus files you downloaded have correct SHA1 checksum." How do I check this? Could you share the steps.

Thank you,
Best Regards.

[RongYuan]

In Quartus tool download website, you can find a SHA1 checksum like below screenshot. In linux, you can use command shasum to check if your download file is broken or not. Incomplete tool may cause some unexpected issues while using.

Regards,

Rong

[RongYuan]

Please choose "F-Tile Avalon Streaming Intel FPGA IP for PCI Express" in IP catalog.

"AXI Streaming Intel FPGA IP for PCI Express" is for R-Tile, not for your target device.

Regards,

Rong

[FPGA_Mozart]

Hello Rong,

Intel OFS Design for the fseries-dk uses AXI Streaming Intel FPGA IP for PCIe for the F Tile devices. 
I have already used this IP in an R31B (4 Ftiles) Based FPGA. 
I want to generate one for the R24C device.

Thank you,
Regards

[RongYuan · Accepted solution]

In Q24.1 the design example generation is only for P-Tile and R-Tile.

You can simply instantiate one IP in your project or copy that IP from your previous project.

Regards,

Rong

[FPGA_Mozart]

Hi Rong,

It is alright. I wanted to generate the example design to Validate AXI Streaming Intel FPGA IP for PCI Express in my device.
But it is alright. I will use the previous project on this device.
You can close this case now.

Thank you,
Best Regards.