Community
cancel
Showing results for 
Search instead for 
Did you mean: 
Altera_Forum
Honored Contributor I
807 Views

Unable to get 64 bit PCIe Address Headers ( only 32bit addresses are possible )

Hi. We have to a PCIe HIP Root Port in a Cyclone V FPGA. We need to use 64 bit addressing to support the needs of our project. We are using the Avalon-MM interface connection , x 4 lane and are operating Gen 1 speed. We have a PCIe analyzer connected the PCIe bus so we can view PCIe traffic. The PCIe HIP seems to be working in all manners other than not be able to output a 64b address header even when the 64b Tx Avalon-MM address input has an address > 4GB and was confirmed with signal tap analyzer. The lower 32b Avalon-MM address input are accurately sent out on the PCIe bus. The attached file PCIe HIP GUI Setup.jpg show the settings we are using for the PCIe HIP. Any suggestions on a solution would be greatly appreciated. Thanks .. Larry

Tags (1)
0 Kudos
5 Replies
Altera_Forum
Honored Contributor I
83 Views

There is a Knowledge Base entry that might be helpful to you: 

 

http://altera.co.uk/support/kdb/solutions/rd05272014_431.html
Altera_Forum
Honored Contributor I
83 Views

Some additional information/comments to go with first post 

 

We are unable to write ( change) the Prefetchable Memory Limit and Prefetchable Memory Base field in the Root Port Type Configuration Register ( 24h) .  

Read back of Configuration Register 24h results in 0x00000000. Thus, the nibbles which indicates 32b or 64b operation is set to 32b for both the Prefetchable Memory Limit and Prefetchable Memory Base 

 

There is no field in the PCIe HIP Avalon-MM GUI to set the Prefetchable memory size ( Disable, 32b address, 64b address), unlike the Function 0 tab in the PCIe HIP Avalon- ST GUI. 

 

We do have the field of " Address Width of Accessiable PCIe memory space" in the PCIe HIP Avalon-MM GUI set to 64 . 

 

Thanks 

 

Larry
Altera_Forum
Honored Contributor I
83 Views

We are having a similar problem in both regards with a Cyclone V HIP PCIe Avalon MM endpoint, Gen 1x1. When we request a 64-bit address >4GB, the Slave i/f (TXS) on the PCIe accepts the request but when you capture the TLP that gets generated it is a 32-bit Memory Read Request TLP and with the upper 32-bits zeroed out. 

 

We are also having problems accessing the CRA registers as when I do a read dump all data comes back 0's. However It appears that I can write the CRA because for 64-bit addressing and MSI-X capability you have to set bits 2 and 3 in the cmmd reg (offset x04). I wasn't able to generate an MSI-X until I set these bits so it must have accepted them at least one of them.  

 

I have open SRs on both these issues with Altera but no solution as of yet. In the meantime, for the CRA issue you might want to check out solution ID rd03062014_662 if you haven't done so already. It didn't work for me but others have said it does. Hope this is a configuration issue and not systemic. Good luck.
Altera_Forum
Honored Contributor I
83 Views

Awesome LBERNSTEIN, that did the trick!

Altera_Forum
Honored Contributor I
83 Views

evangelosa, Thank you so much for suggesting that we check out this recent post on the UK forum http://altera.co.uk/support/kdb/solu...72014_431.html 

We followed the workaround instructions and we now have 64b PCIe addresses/4 DW header TLPs when address is > 4GB . I think we are all set.. Larry
Reply