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Valued Contributor III
818 Views

Unable to place and Route altera_iopll in my design with Quartus 16.1 Pro Edition

Hi, 

 

I have a design which uses altera_iopll. I'm trying to synthesize the design using Synplify_Premier 2016.09-SP1 and Place & Route using Quartus 16.1 Pro Edition. I'm able to generate the .vqm file from Synplify_premier. However, I'm unable to PnR my design using Quartus due to following error: 

Error(13411): Verilog HDL syntax error at near text  

Error(16814): Verilog HDL error at altera_iopll.v(68): unknown literal value for parameter clock_name_1 ignored  

Error(13411): Verilog HDL syntax error at near text  

Error(16814): Verilog HDL error at altera_iopll.v(69): unknown literal value for parameter clock_name_2 ignored  

Error(13411): Verilog HDL syntax error at near text  

Error(16814): Verilog HDL error at altera_iopll.v(70): unknown literal value for parameter clock_name_3 ignored  

.<Error Continues - and all the errors are similar to above> 

My filelist to Synplify was just <pll_dir>/synth/<generated_iopll_top.v> and <pll_dir>/altera_iopll_161/<generated_iopll_top>_altera_iopll_161_lx6audi.v 

and in the Project options i have choosen Quartus version also as 16.1. This is creating .vqm as expected by making altera_iopll instance in the <pll_dir>/altera_iopll_161/<generated_iopll_top>_altera_iopll_161_lx6audi.v blackbox whih will be later inferred automatically during PnR by Quartus. 

 

Also, I have noticed that, if I use Quartus 15.1 Std Edition instead of 16.1 Pro Edition for generating PLL and PnR, I can run both Synplify_premier and Quartus successfully. 

 

Any suggestions on what could be the reason for Quartus 16.1 to throw up those errors during PnR? 

Thanks in advance. 

 

Regards, 

pcs
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2 Replies
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Valued Contributor III
20 Views

Hi psc, 

 

there is an issue with the iopll in Quartus Prime Pro 16.1, if you are in urgent need of help you will have to contact the Altera support otherwise use the older releases or wait for the next patch. 

 

Cheers, 

fade
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Valued Contributor III
20 Views

Hello Fade, 

 

Thanks for the response. Now, I'm using _bb.v (blackbox models) for the IOPLL's during Synthesis and including their .qsys files during PnR. This has solved the issue for me. 

 

Regards, 

Poorna
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