I have been trying to implement the UniPHY memory controller for DDR2 SDRAM (Micron MT47H64M16HR-25E) in a Stratix 3 part (using EP3SE260F1152C2) for months. I pulled out everything except the example design and some logic to keep parts on my board (custom design by me) from contending. The design compiles and indicates that it meets timing (TimeQuest Report DDR), but when I program it into my board, it indicates that the test is complete, that it failed, and that calibration failed. I have 50 ohm resistors on the rup and rdn pins that Quartus used and have assigned pins in banks 2A, 3A, and 3B in accordance with the data sheet. The way I have implemented the design, I am using 2 of the SDRAM parts organized as 32 bits wide, using the same addresses, RAS, CAS, and WE for both but separate clocks, ODTs, chip selects, CKEs. I have even attempted to use the EMIF toolkit to debug this but it shows that it fails calibration, the failing stage is read calibration - VFIFO (I can't figure out where that is on the block diagram), failing DQ group 0, but then it indicates that post calibration test passes (??!!). I am not making any progress on this. Does anyone have any ideas of what else to try?
Marie
