Uniphy DDR3 controller waitrequest simulation problem/How to simulate Uniphy memory

[Altera_Forum]

Hello everyone, 

 I am trying to simulate the DDR3 Uniphy memory controller I have just created in Qsys(see screenshot) and I am running into the following problem:  At the beginning, the waitrequest_n signal is low, which is ok, the module needs time to initialise. Then it goes high, meaning that the module is usable, however, after just a few cycles it goes low again and doesn't change after that.  What I think why it may be doing this, is that the simulator does not know there should be a memory connected to this module, the FIFO fills up after just a few datas arrive and stays that way as nothing is there to remove the data from the FIFO. But I am unsure that this is really the problem.  I have used an On-Chip memory module before, and I need to replace it with a Uniphy controller, as I just need more space. How do I go about simulating external memories so they work similarly to their on-chip counterparts? I have looked at the reference design(Cyclone V, as that is my device) of the module, but they weren't really helpful. I have also looked at Section II. UniPHY Design Tutorials : External Memory Interface Handbook Volume 5; but I haven't found the memory model or the driver mentioned there.  Thank you and Best Regards,  Tibor

[Altera_Forum]

Try generating the example design from the UniPHY IP Parameter Editor. This includes a traffic generator and a generic memory model based on the parameters you specify. If you want to simulate with the specific memory on your board, you can usually download a simulation model from the vendor of the memory and add it to your simulation testbench. 

 This training is a little old, but it does include steps and a demonstration about simulating the interface: https://www.altera.com/support/training/course/omem1110.html

[Altera_Forum]

Hello, 

 Thanks for your answer, I have gone through the training course, tried generating an example design, it compiled and did the simulation. Unfortunately, as soon as I tried to compile the testbench generated by Qsys, it failed with the the error message: "Altera DDR3 Memory Model for UniPHY does not support the QUARTUS_SYNTH fileset".  Then I tried downloading the simulation model from the vendor of the memory. However, the simulation model has SystemVerilog parts and thus the compiler of Quartus-Modelsim Starter Edition does not recognise some parts of it, so I cannot even try it out. I simply do not now where to get an usable model I can use for simulation. The problem is, that the SystemVerilog part is right in the memory model, not even in the testbench.  Where or how can I get a usable simulation model in this case?