FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP

Unresolved module

Honored Contributor II

Hi All, 


1. I created a new custom megafunction variation ALTPLL and created a Verilog HDL file (e.g. ALPLL0.v and ALPLL0_0002.v). 


2. I tried to compile the Verilog HDL file using VCS. 


3. I encountered an error regarding Unresolved module pointing to altera_pll.v inside ALPLL0_0002.v. 


Question: Do I still need to add a path to resolve this? Or I' am missing something during creation of new custom megafunction variation? 


BTW I'am using Arria V 


Many Thanks in advance, 

FPGA Newbie
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