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User Auto-Refresh Conduit with hard memory Controller. Strange request behaviour?

Honored Contributor II

Hi all, 

I have an FPGA application which needs the DDR3. 

I am able to write and read through the MPFE (Multi-Port Front End) but I have some criticial timing therefore I want to handle the refresh by myself. I checked the User Auto-Refresh controls and the conduit is there. 


So, when I know that there is enough time to do a refresh, I simply set the local_refresh_req to high/1 and wait for the local_refresh_ack to get high. Besides that, the chip signal is also set to the right value. But that never happens. 

The acknowledgment through the local_refresh_ack only gets to a high/1 value, if I oscillate the request signal from 0 to 1 and the next clock cycle from 1 to 0 until the acknowledgment is high. At this point, I stop to oscillate and a refresh really happens at the DDR3. 


Why do I need to do that? I thought that it would be much more intuitive if the request signal can be assigned to 1 until I receive an acknowledgment. And I can not even find something in the documentation which descirbes this behaviour. 


Any ideas if I am doing something wrong or experience with the User Auto-Refresh controls? 


All this happens in the simulation. Never tested that on the real board because there is some other work to do before it can be tested on the board. 


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2 Replies
Honored Contributor II

What device are you using? How long are you giving it after asserting the request and watching the acknowledge? When I've used it in the past, it behaved the way I expected.

Honored Contributor II

Thanks four your reply. 


Currently I am using a Cyclone V device. You need to keep in mind that this happens in simulation with ModelSim. 


When my custom logic tells me that every request is passed to the controller, I assert the request. Kept watching for an acknowledgment for about 5000 clock cycles and still no acknowledgment. 

If I use the oscillation on the request signal, which basically looks then like a half rate clock in the waveforms, I get the acknowledgment after 10 or 12 clock cycles. 


To me it looks like the controller is ignoring the first refresh requests because it needs to deal with the read and write requests. And it looks like the controller only checks for rising edges on the local_refresh_req signal, otherwise there would be no different behaviour between a constant high signal, which never leads to an acknowledgment, and a oscillating singal, which leads to many rising and falling edges on the req signal until the acknowledgment is received.