Using Altera PLL make 500Khz or below

[jjang]

When i Using ALTPLL, i Usually make 500khz and below xx kHz Frequency Clock. @ 50Mhz  / 100Mhz Input clock.

But Cyclone 5,  Different PLL IP Core. 

 - ALTPLL → Altera PLL,  so it doesn't support for Low Frequency Clock.

 does have any way to make 500kHz or 10kHz frequency Clock? 

[FvM]

Hi,
all Intel FPGA starting with Cyclone III have a post-scale counter cascading feature and can generate output frequencies down to a few kHz, also Cyclone V.

Regards,
Frank

[jjang]

As Clocking and PLL User Guide.. 

Using PLL Clock (C1, C2. C3.C4), then that can though Global clock.

but to make a Clock as  a Logic (such as Counter).. will not connect to Global clock . .isn't it?

[FvM · Accepted solution]

Hi,
just read PLL Intel FPGA IP messages thoroughly. It instructs you to enable physical output clock pararameters to configure cascaded output counters.

[AqidAyman_Intel]

Hi,

I wish to follow up on this issue. Have you able to use the cascading feature to generate the low frequencies output clock?

Regards,

Aqid