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Hi All,

I have questions about this designe example: http://www.altera.com/support/examples/dsp-builder/exm-cic-decimation-filter.html I have attached the design files. In the file fir_compiler_v7_2.vhd, it goes "number_of_input_channels" value="2" "input_bit_width" value="16" "output_bit_width" value="35" So the two input channels of fir conveys 8-bit 'I' and 8-bit 'Q' data respectively (correct me if it is wrong). Does that mean 'I' and 'Q' are merged into 35-bit packet on the output interface so the first half contains 'I' and the second half has 'Q'? Then the 35-bit output is sent to Avalon-ST Packet Format Converter. The converter seperates the 35-bit 'IQ' packet into two sources, 35-bit 'I' and 35-bit 'Q'. Does the converter perform the bit extension to add more bits to I and Q outputs, respectively, to have the bit width of 35? Many Thanks, LeeLink Copied

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Hi Kaz,

You mentioned "I and Q are interleaved at FIR output". What does interleaved mean? Does that mean there are two output channels for 35-bit I and 35-bit Q, respectively? Thanks, Lee- Mark as New
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Hi Kaz,

I'm trying to run the simulink model CICDownMISO.mdl but I re-created the model using 13.1 version of CIC and FIR compilers and re-named it as CICExample.mdl. I have attached the file. In the Step bolck, it has the parameter Sample time: clock1. I got an error saying undefined variable clock1. How do I define clock1 in the model? I'm very new to Simulink DSP Builder. Thanks, Lee- Mark as New
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The assignment of variable clock1 can be found here:

In the Simulink model, File->Model Properties -> Callbacks (Tab) -> InitFcn* (Model Initialization Function)-> clock1 = 1; ....- Mark as New
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Hi All,

How to decide the bit width for the fir filter coefficient? Is the bit width the same as the input data bit width? Many Thanks, Lee- Mark as New
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