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Altera_Forum
Honored Contributor I
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Using DSP block for CRC calculation

I'm wondering if there is a way to utilize DSP blocks for CRC calculation.  

Typically, parallel or serial CRC is implemented as XOR trees. But perhaps there is an algorithm to do it with adders and multipliers. 

 

My designs have multiple CRC32 with 512- and 1024-bit datapaths, running at 250MHz and higher speeds. They consume huge amounts of logic and very tight on meeting timing. Whereas lots of FPGA DSP blocks are sitting unused. 

 

Thanks, 

Evgeni
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Altera_Forum
Honored Contributor I
79 Views

 

--- Quote Start ---  

I'm wondering if there is a way to utilize DSP blocks for CRC calculation.  

Typically, parallel or serial CRC is implemented as XOR trees. But perhaps there is an algorithm to do it with adders and multipliers. 

 

My designs have multiple CRC32 with 512- and 1024-bit datapaths, running at 250MHz and higher speeds. They consume huge amounts of logic and very tight on meeting timing. Whereas lots of FPGA DSP blocks are sitting unused. 

 

Thanks, 

Evgeni 

--- Quote End ---  

 

 

 

CRC is a simple XORing bits it has to be computed using XOR this is fastest way to do it , DSP Blocks handle min 8-bits of data being added and multiplied . 

Where as in CRC you have to do that 1-bit at a time . 

 

Ahmed Asim Ghouri 

Embedded Strings inc 

Website : www.emstrings.com (http://www.emstrings.com

Email : support@emstrings.com
Altera_Forum
Honored Contributor I
79 Views

Will answer my own question. 

After doing some research, the answer is no. It's not possible to use regular additions and multiplications in Altera DSPs for CRC calculations.  

CRC calculation uses polynomial arithmetic over finite GF(2) fields, described here: http://en.wikipedia.org/wiki/finite_field_arithmetic 

 

As a matter of fact, Xilinx DSP48 blocks do support polynomial arithmetic to some extent (XOR and other operations). 

 

Thanks, 

Evgeni
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