Using UART at arbitrary BAUD Rate

[Altera_Forum]

I am using QSYS on the MAX10. I am interfacing to another board over an LVDS Physical Layer using a UART. The data rate is 80 MHZ. I am planning on oversampling at a clock rate 4x the data rate ie 320 MHz. 

How can I do this? Can I do this using the altera_up_avalon_rs232 or     altera_avalon_uart   

[Altera_Forum]

I would write a custom UART for this. I seriously doubt any Altera IP would let you run that fast or with 4x oversampling unless you did some major hacking. At that point I think it's easier to start from scratch. Or find a free UART example and modify that.

[Altera_Forum]

--- Quote Start ---  I would write a custom UART for this. I seriously doubt any Altera IP would let you run that fast or with 4x oversampling unless you did some major hacking. At that point I think it's easier to start from scratch. Or find a free UART example and modify that.  --- Quote End ---     Thanks. I was originally going to use the MINIUART from Opencores, but I figured that if Altera already has the IP I might as well use it. It will support a 4x oversample so I just have to map the wishbone to the Avalon-MM. It would be nice o be able to drop in the IP though.

[Altera_Forum]

--- Quote Start ---  I am using QSYS on the MAX10. I am interfacing to another board over an LVDS Physical Layer using a UART. The data rate is 80 MHZ. I am planning on oversampling at a clock rate 4x the data rate ie 320 MHz. How can I do this? Can I do this using the altera_up_avalon_rs232 or altera_avalon_uart  --- Quote End ---    You are going to have serious problems getting any compiled design to run at 320MHz on the MAX 10 device. This is operating at the very high end of the PLL clock tree generator output (depending on speed grade) and any logic you want to run at 320MHz will likely need to be hand generated and placed to be able to come anywhere close to meeting timing.  I think you need to rethink your communication architecture and not use 4X oversampling but rather some type of DDR clocking protocol.