The memory blocks internal to FPGA's do not typically have a clearing function that zeros the memory locations, but rather clear output registers that hold the last value read, or address latching registers for holding addresses, etc.Refer to the sevtion fo the particular families data sheet for details on these clearing functions. As such, most inferred RAM do not see a need for the reset function.
Yes, the megawizard generates a vhdl file. But, in my design project I can not use a generated component because each ligne VHDL wrote must be justified.So, a generated component has a supplementary code. In my design, I do not like to use the ALTERA labrary, too.