FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP

Using the ADC IP core

Honored Contributor II



I'm using the ADC IP core for the first time in my design on MAX10. I have initiated the IP core in the Qsys and selected the core variant as ADC core control only and have set all the parameters. I have enabled the ADC1 CH0 and all the other channels have been disabled. I am using a signal generator to give the external signal to the ADC pin present in the board. I'm bit confused over here how to map the external signal given to the pin to the input data of the ADC IP core. Can anyone please help me with this ? 


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