V Series Native Phy Simulation

[JLee25]

Hi,

I am using the CV Native Phy Manual Align BYTE Order Double Width as a template for my requirement.

I modify the phy ip parameter and run the simulation.

But looks like Word Aligner and Byte Ordering is not working.

I

Perhaps I missed something in my design.

Would you advice me how to do it properly?

Thank you!

BRs,

Johnson

[Deshi_Intel]

HI,

You can checkout below example design as reference

• https://forums.intel.com/s/createarticlepage?language=en_US&articleid=a3g0P0000005QydQAE&artTopicId=0TO0P000000MWKBWA4&action=view

Thanks.

Regards,

dlim

[JLee25]

Hi Dlim,

Thank you!

If I want to following those references and generate mine, do you know where I can find information or instructions?

BRs,

Johnson

[Deshi_Intel]

HI Johnson,

Sorry, I don't understand your request here.

May I know what do you mean by "where I can find information or instructions" ? Can you elaborate further ?

• Are you looking for instruction on how to use Quartus or How to use NativePHY IP or something else ?

Thanks.

Regards,

dlim

[JLee25]

Hi Dlim,

I want to know about how I can use Native Phy and how to do simulations like your references in the link you provided. ​

Thank you. ​

BRs,

Johnson ​

[JLee25]

Hi Dlim,

Based on the reference project I received, I made some modifications to meet my requirement.

Data rate to 2.7Gb​ with 20-bit PMA/ PCS interface.

Then I started simulation and found the manual Word Aligner mode is not working properly.

I suppose the word aligner should align to 17C but no response as below.

Would you review and give me suggestions?

I attached here for your check.

Thank you!

BRs,

Johnson

[Deshi_Intel]

HI Johnson,

Pls give me sometime to review both the example design and your modified design.

Btw, byright you should be using "Cyclone V Native PHY with manual alignment and byte ordering in double width mode design example" that's closer to your design requirement but your attached design is the 8b10b example design instead ?

Have you try out and cross check with the double width example design without the 8b/10b ?

Thanks.

Regards,

dlim

[JLee25]

Hi Dlim,

Thanks for getting back.

Please forget the previous attachment project.

I am generating another one because I found an error when generating the native phy ip with device.

I will ask more questions later.

BRs,

Johnson

[Deshi_Intel]

Alright, keep me posted then

[Deshi_Intel]

Hi Johnson,

It's been sometime since I last heard from you on this case update. I guess you are still working on it.

For now, I am closing this case first as I can't let the case idle for too long.

You are always welcome to file new forum case for continuous support from Intel agent whenever you are ready to present your issue in future.

Thanks.

Regards,

dlim