VHDL-Code with Avalon Bus Interface-/ and VHDL-Video-System-Interface-Ports

[Altera_Forum]

Hello  

I provided the following ENTITY. Can I actually provide a IP, which some haven connectivity with the Avalon bus, as well as haven as down descriptive for the VHDL_Detector, which is not connected with the Avalon bus, but with the video system, which was evenly not provided in SopC?   We provide as it were 2 different systems, the Video_System as own symbol and the SopC system also as own symbol.   These 2 different systems can communicate however by the VHDL_Detector via Avalon bus with one another.     -- VHDL_Detector Clock interface  iVGA_CLK : in std_logic;   iRST_N : in std_logic;   -- VHDL_Detector of In-haven   iVGA_R : in std_logic_vector (9 downto 0);   iVGA_VS : in std_logic;     This haven are connected with the video system.       -- Avalon Clock interface   csi_clock : in std_logic;   csi_reset : in std_logic;   -- Avalon mm of interfaces/Slave haven   avs_write : in std_logic;   avs_writedata : in std_logic_vector (31 downto 0);   avs_read : in std_logic;   avs_readdata : out std_logic;   avs_dataavailable : out std_logic;   avs_byteenable : in std_logic_vector (3 downto 0)     This haven are connected with the SopC.  **********************************************************************************  ENTITY ime_avalon_xy_detector IS  PORT  (  -- VHDL_Detector Clock Interface  iVGA_CLK : in std_logic;  iRST_N : in std_logic;  -- VHDL_Detector IN-Ports  iVGA_R : in std_logic_vector(9 downto 0);  iVGA_VS : in std_logic;  -- Avalon Clock Interface  csi_clock : in std_logic;  csi_reset : in std_logic;   -- Avalon-MM Interface / Slave Port  avs_write : in std_logic;  avs_writedata : in std_logic_vector(31 downto 0);  avs_read : in std_logic;  avs_readdata : out std_logic;  avs_dataavailable : out std_logic;  avs_byteenable : in std_logic_vector(3 downto 0)  );  END ENTITY ime_avalon_xy_detector;

[Altera_Forum]

>> -- VHDL_Detector Clock interface 

>> iVGA_CLK : in std_logic;   >> iRST_N : in std_logic;   >> -- VHDL_Detector of In-haven   >> iVGA_R : in std_logic_vector (9 downto 0);   >> iVGA_VS : in std_logic;   >>   >> This haven are connected with the video system.   or can I declare this ports as conduit-ports and make a connection from the SopC-Symbol to the Video-System-Symbol?  The goal to make this connectivity, is to send a xy-cordinate from a object-detection to a steppmotor controller via SPI in SopC.  Thanks for any answer..... :)

[Altera_Forum]

here is a little schematic for better understanding my project... 

 :D

[Altera_Forum]

In general, you have part of your component that attaches to the sopc system via some avalon style bus, and then you have the other part that are defined in the *_hw.tcl file as conduits. Just define everything you want to connect not in the sopc system as conduits and hook them up outside of the sopc generated block. Give it a try and see what happens.

[Altera_Forum]

Hello, 

Thans for the answer. I realize a IP, you see this in the .zip-file below. In the NiosII I have write a simply test-code for send any data via avalon-slave bus and after read the data again. In the example I send the data= 0xF0F0F0F0, but I receive the follow:  Der gelesene Wert ist: -252645136  The code in NiosII is: # include "NiosII_Camera_Tracking.h"   int main(void) {  alt_u32 daten= 0xF0F0F0F0;    IOWR_IME_AVALON_XY_DETECTOR_DATA(XY_DETECTOR_BASE, daten);    printf("Der gelesene Wert ist: %i\n", IORD_IME_AVALON_XY_DETECTOR_DATA(XY_DETECTOR_BASE));   }     Could you test the IP-Block and say me what is the problem?  Thank you...

[Altera_Forum]

change the print statement to : 

 printf("Der gelesene Wert ist: %x\n", IORD_IME_AVALON_XY_DETECTOR_DATA(XY_DETECTOR_BASE) );  you were reading an unsigned int as a signed int. -252645136 is equal to 0xF0F0F0F0;  Kevin

[Altera_Forum]

thanks a lot, it works well now... 

  :D:D:D:D

[Altera_Forum]

I have another question: 

I would like read the xy-coordinate only when a new frame is coming and the vhdl-hardware have calculate the new coordinate. I think to make this as follow:  I implement a avs_dataavailable in the ip-block, when a new calulation is down, a set the avs_dataavailable to H. But how is the syntax in NiosII to make this if-statment?  Thanks for any tipps....

[Altera_Forum]

you don't want to use the avs_dataavailable signal. Either create an interrupt that is triggered on the new state, or create a register you can read/poll that has the status of the new coordinate state that can be cleared when you read it. i have never used the dataavailable signal, but if you were to use the avalone bus to indicate when data was ready to read you would have to issue a read and the bus would hang until the new coordinate was present, which is most likely not what you want.  

 Kevin

[Altera_Forum]

do you mean so for example: 

     dataavailable = IORD_IME_AVALON_XY_DETECTOR_CONTROL(XY_DETECTOR_BASE, 1)    if(dataavailable)   {  coordinate= IORD_IME_AVALON_XY_DETECTOR_DATA(XY_DETECTOR_BASE, 0)  }     and the reg.h:    # define IOADDR_IME_AVALON_XY_DETECTOR_DATA(base, offset) __IO_CALC_ADDRESS_NATIVE(base, 0)  # define IOWR_IME_AVALON_XY_DETECTOR_DATA(base, offset, data) IOWR(base, 0, data)  # define IORD_IME_AVALON_XY_DETECTOR_DATA(base, offset) IORD(base, 0)     # define IOADDR_IME_AVALON_XY_DETECTOR_CONTROL(base, offset) __IO_CALC_ADDRESS_NATIVE(base, 1)  # define IOWR_IME_AVALON_XY_DETECTOR_CONTROL(base, offset, data) IOWR(base, 1, data)  # define IORD_IME_AVALON_XY_DETECTOR_CONTROL(base, offset) IORD(base, 1)   . . . here MSK and any OFST . . .     Antonio

[Altera_Forum]

another question: 

 How I can differentiate in the vhdl-file in where Signal I wont write or read, when I use two register for DATA and CONTROL specificate in the reg.h? I have only a avs_writedata in the vhdl-file....:confused:

[Altera_Forum]

you need an avs_address, avs_read, avs_write signals. Your address will be however many spots you need, which sounds like only 1, so it can be a std_logic rather than a std_logic_vector. Then when the avs_write is strobed you look at the address to see who you are writing to. Same for the read. your reg.h file is generally correct, but can be simplified: 

  # define IORD_IME_AVALONE_XY_DETECTOR_DATA() IORD(XY_DETECTOR_BASE,0) # define IOWR_IME_AVALONE_XY_DETECTOR_DATA(data) IOWR(XY_DETECTOR_BASE,0, (data)) # define IORD_IME_AVALONE_XY_DETECTOR_CONTROL() IORD(XY_DETECTOR_BASE,1) # define IOWR_IME_AVALONE_XY_DETECTOR_CONTROL(data) IOWR(XY_DETECTOR_BASE,1, (data))   Not sure if you want 1 or 4 for the offset of the second one. I have never really used the IO_CALC_ADDRESS_NATIVE functions as I always use 32-bit slaves with 32-bit masters, so the offset is always 4.   Help?  Kevin

[Altera_Forum]

Thanks Kevin, this help me well. 

 But now I have another problem:  Here the complete vhdl-code:   LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; USE ieee.numeric_std.all;  ENTITY ime_avalon_xy_detector IS  PORT   (  -- Avalon Conduit to VHDL_Detector Clock Interface  coe_iVGA_CLK : in std_logic;  coe_iRST_N : in std_logic;  -- Avalon Conduit to VHDL_Detector IN-Ports  coe_iVGA_R : in std_logic_vector(9 downto 0);  coe_iVGA_VS : in std_logic;  -- Avalon Clock Interface  csi_clk : in std_logic;  csi_rst_n : in std_logic;   -- Avalon-MM Interface / Slave Port  avs_address : in std_logic;  avs_write : in std_logic;  avs_writedata : in std_logic_vector(31 downto 0);  avs_read : in std_logic;  avs_readdata : out std_logic_vector(31 downto 0)  ); END ENTITY ime_avalon_xy_detector;  -- ARCHITECTURE rtl OF ime_avalon_xy_detector IS  SIGNAL coordinate_wr : std_logic_vector(31 downto 0); SIGNAL coordinate_rd : std_logic_vector(31 downto 0); SIGNAL x : std_logic_vector(15 downto 0); SIGNAL y : std_logic_vector(15 downto 0);  SIGNAL dat_0 : integer range 0 to 1000000 := 100000; -- 0x186A0 SIGNAL dat_1 : integer range 0 to 1000000 := 111111; -- 0x1B207  BEGIN    write_proc: process(csi_clk, csi_rst_n)  begin    if csi_rst_n = '0' then  coordinate_wr <= (others => '0');   x <= (others => '0');  y <= (others => '0');  elsif rising_edge(csi_clk) then  if avs_write = '1' then  coordinate_wr <= avs_writedata;  end if;  end if;    end process write_proc;        read_proc: process(csi_clk, csi_rst_n)  begin    if csi_rst_n = '0' then  coordinate_rd <= (others => '0');  avs_readdata <= (others => '0');   x <= (others => '0');  y <= (others => '0');  elsif rising_edge(csi_clk) then  coordinate_rd <= coordinate_wr;    if avs_address = '0'then  coordinate_rd <= std_logic_vector(to_unsigned(dat_1, 32));  elsif avs_address = '1' then  coordinate_rd <= std_logic_vector(to_unsigned(dat_0, 32));  end if;    if avs_read = '1' then  avs_readdata <= coordinate_rd;  end if;  end if;  end process read_proc;  END ARCHITECTURE rtl;       in this case the NiosII can not load the prgram in ram. Here the messagge:  Verifying 00080000 ( 0%) Verify failed between address 0x80000 and 0x8D0DB Leaving target processor paused   but when I change the part with the avs_address as below:  if avs_address = '0'then  coordinate_rd <= std_logic_vector(to_unsigned(dat_0, 32));  elsif avs_address = '1' then  coordinate_rd <= std_logic_vector(to_unsigned(dat_1, 32));  end if;    the NiosII will work good. Thats very strange.....  Have you any idea???????

[Altera_Forum]

here is the code in NiosII: 

 # include "NiosII_Camera_Tracking.h"   int main(void) {  alt_u32 daten= 0xF0F0F0F0;    IOWR_IME_AVALON_XY_DETECTOR_DATA(XY_DETECTOR_BASE, daten);    printf("Der gelesene Wert ist: %x\n", IORD_IME_AVALON_XY_DETECTOR_DATA(XY_DETECTOR_BASE));    printf("Der gelesene Wert ist: %x\n", IORD_IME_AVALON_XY_DETECTOR_CONTROL(XY_DETECTOR_BASE));    printf("Hello World\n"); }

[Altera_Forum]

Where do you set the value of dat0 and dat1? or are you just writing some temp code for now that keeps them constant? 

 Where are you setting x and y? i am surprised what you have compiled because you set them in two different process statements.  Also, the readdata is most likely 1 clock off, as there is a 1 clock delay from when coordinate_rd is set the the correct address value and then another clock till when readdata is set. I would eliminate the coordinate_rd register and just say:   if (avs_read = '1') then if (avs_address = '0') then coordinate_rd <= std_logic_vector(to_unsigned(dat_0, 32)); else coordinate_rd <= std_logic_vector(to_unsigned(dat_1, 32)); end if; end if;   Also, is there a need to use integers rather than unsigned type? in general it is better to use unsigned because you know the size of the variable.    Besides that, no clue why the change in what you return will change the program from being able to load. I could see the your code not working correctly, but i don't really see why it would fail to load the program into memory. Maybe your *_hw.tcl file is wrong and messes up the bus transactions. You are not trying to load program memory into this hw block i assume, but that would cause a problem.

[Altera_Forum]

thanks you from help. But now I make the avalon bus otherwise. 

I changed the reg.h file. I use only a Register with only a address. when the x/y coordinate are ready to read, I send a Interrupt via coe_oCOORD_IRQ to PIO-Interface. This Methode works well.  But when I incontre other problems, I post it for any good suggest from you...  Antonio