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Altera_Forum
Honored Contributor I
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VHDL output given when Verilog requested

Hi 

 

I'm currently going through the motions of getting a DDR3 controller for the Arria II GX development board. 

 

I'm using Quartus 11.0 and I've used the MegaWizard thing to generate the RTL an appropriate controller. 

 

However, even though I asked for Verilog HDL, I get one VHDL file, with the suffix phy_alt_mem_phy_seq.vhd 

 

This file looks pretty serious (14k lines.) My feeling is that there is no choice for this particular file, and you get it in VHDL whether you like it or not. 

 

It's not a major issue for me, but it could also be a bug with this IP generator. 

 

So I'm asking for clarification on whether this is to be expected. If not, then I guess this is a bug and I can provide more information if needed. 

 

It's not critical that I have this module in Verilog, it's just annoying because I have scripts that automatically pick up all the Verilog and pull it into the simulator, but now I have to make an exception for one single VHDL module. I guess this is just the way of EDA. 

 

Thanks for any info. 

 

Julius
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Altera_Forum
Honored Contributor I
41 Views

The primary interfaced module should be Verilog, if requested, but it's only a wrapper. The IP core consists of a number of files, that may be either Verilog or VHDL, depending on the respective Altera Megafunctions. 

 

For a functional simulation, you need to use special simulation files that are replacing the encrypted part of the IP core.
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