VHDL simulation of Uniphy DDR3 controller

[Altera_Forum]

Hello, 

 I have no idea what I'm doing wrong. I'm generating a VHDL DDR3 Uniphy controller with the MegaWizard (Quartus 10.1).  I wanted to simulate the example design, but I 'm running into 2 problems: - all testbench files in <variation_name>_example_design_fileset folder are Verilog only (including testbench top, example driver, ...) - the simulation oriented version of the controller <variation_name>_sim folder is a VHDL file (an encrypted .vho file), but it does not compile correctly in ModelSim!  Did anyone succeed in simulating Uniphy in VHDL language?  Note: of course I don't have a Verilog license available for ModelSim.  JC

[Altera_Forum]

this was an issue 10.0, but was supposed to be fixed in 10.1: 

 http://www.altera.com/literature/rn/rn_ip.pdf  maybe the work around provided in the errata will help

[Altera_Forum]

Thank you for pointing me to this errata list. 

 According to this list, the root cause of my problem is that I should not use the half rate bridge feature (feature that allows to implement a local interface with half the rate of the clock sent to the memory device). Unfortunately, the document states that: - The half rate bridge feature is not supported by Quartus 10.1 - The half rate bridge feature is supported by Quartus 10.0, but attempts to generate a VHDL IP leads to verilog files.  This means that UniPHY is not a usable option for me yet.  I'll switch back to a good old ALTMEMPHY solution then ...