FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
6351 Discussions

VIP Frame Buffer/Deinterlacer base address parameters

Altera_Forum
Honored Contributor II
1,073 Views

Hi gents, 

I am some confused with base address parameter of Frame Buffer/Deinterlacer IP core. SDRAM controller have 64bit data width and 25-bit address width on avalon side. Frame Buffer/Deinterlacer also set to 64 bit data width. I have two frame buffers and one deinterlacer connected through the MM_bridge with following parameters : data width 64 bit, address width 25 bit, address units - words. So, should I specify base adress offset in bytes or in 64-bit words? I'm trying to optimize memory usage and faced with picture overlapping if I set offsets in 64 bit words. 

 

Regards, 

Sergey Burenkov
0 Kudos
2 Replies
Altera_Forum
Honored Contributor II
268 Views

The base address is in bytes.

0 Kudos
Altera_Forum
Honored Contributor II
268 Views

Thanks, Ted!

0 Kudos
Reply