Hello all,In the VIP suite there is a new Scaler called Scaler II (Quartus 10.1). I had a short try with it and I found that I can not control the output hight through the software (control port) only the width. Anybody know if the register offsets has been changed? The VIP User manual did not update in the Quartus 10.1 so I can not know from it. Thank you in advance, Reuven
Yes, the register offsets have changed. Width is now at address 3 and height is at address 4.I find it a little frustrating that Altera releases updated IP without releasing the documentation.
Thank you Kavin,Yes it is frustrating. Did you just try different address offset till it worked or you found all the register map of the Scaler II? BR, Reuven
I have been using a beta release of Scaler II since before Quartus 10.1 was released. The beta release included documentation.If you are desperate to use Scaler II and need more info, you may be able to get the documentation from Altera support or ask your FAE. I am not sure if I am allowed to send the beta documentation to you.
Kevin,I understand it is OK. I just wanted to know if the documentation is on the website and I do not know how to find it? At the moment I can manage with the Scaler, but I will wait for the Scaler II (documentation and C++ API) in order to benefit from the 4:2:2 processing ability. BR, Reuven
Hi,The C++ API is usually shipped with reference designs or example designs. You will probably have to request the UDX4 reference design (through the Altera website or FAE) to get it.
Here is the register map for the Scaler II. The basic functionality of the Scaler II core is the same as the original Scaler. There are a couple of extra parameters in the GUI, but hopefully there is enough of a description to use these. The updated user guide for 10.1 should be available online by the end of next week.0: control The zeroth bit of this register is the go bit, all other bits are unused. Setting this bit to 0 causes the core to stop the next time that control information is read. 1: status The zeroth bit of this register is the status bit, all other bits are unused. The core sets this address to 0 between frames when the go bit is set to 0. It is set to 1 while the core is processing data and cannot be stopped. 2: reserved This register is reserved for future use. 3: output width The width of the next output frame in pixels 4: output height The height of the next output frame in pixels 5: horizontal coefficient write bank Specifies which memory bank horizontal coefficient writes from the Avalon-MM interface are made into. 6: horizontal coefficient read bank Specifies which memory bank is used for horizontal coefficient reads during data processing. 7: vertical coefficient write bank Specifies which memory bank vertical coefficient writes from the Avalon-MM interface are made into. 8: vertical coefficient read bank Specifies which memory bank is used for vertical coefficient reads during data processing. 9: horizontal phase Specifies which horizontal phase the coefficient tap data in the coefficient data register applies to. Writing to this location, commits the writing of the coefficient tap data. This write must be made even if the phase value does not change between successive sets of coefficient tap data. 10: vertical phase Specifies which vertical phase the coefficient tap data in the coefficient data register applies to. Writing to this location, commits the writing of the coefficient tap data. This write must be made even if the phase value does not change between successive sets of coefficient tap data. 11 to 10 + ntaps: coefficient data Specifies values for the coefficients at each tap of a particular horizontal or vertical phase. Write these values first, then the horizontal phase or vertical phase to commit the write.