VIP Scaler problems....

[Altera_Forum]

Does anyone have any experience of using the Scaler with the megawizard plug-in manager? 

I cant use the sopc builder (for reasons too boring to mention) and I cant get a decent image from the Scaler. I'm reading an image 720x288 from Ram into a Fifo, into the scaler and onto a vga monitor. I've read the image direct from ram to the display and its fine (except a bit small) but when it goes through the scaler it comes out with some lines out of sync. I've spoken to Altera who suggest that there are overflow/underflow or counter errors. I've just spent the whole of this month trying various configurations and debugging and as far as I can tell its perfect....I've tried everything except for the right thing :)  Can anyone help, this is the final piece in the jigsaw for my product.   Thanks

[Altera_Forum]

Could you describe your system in a little more detail? 

1 - What version of the tools and IP are you using? 2 - What FPGA are you using and what speed grade? 3 - You are displaying a static 720x288 image. How many bit per pixel? I assume this is RGB. 4 - You are reading data from RAM. What kind of RAM? How wide is the interface? What speed is it running at? 5 - The FIFO. Is this a single-clock or dual-clock FIFO? How fast are you running it? How deep is it? 6 - The scaler, what algorithm are you using? What is your scaling factor? 7 - You're output block. What are you using as an output block (VIP clocked video output or home-brewed)? How fast are you running it? What is the output standard of the VGA (resolution)? What are your settings for sync, front porch, back porch, etc.?  8 - Do you have any FIFO between the scaler and your output block? 9 - Do you have anything in the Video processing path that inserts VIP control packets (information needed by the scaler to provide input/output resolution). 10 - If you are not using the VIP clocked video output? Do you have anything in the path to remove the video control packets?  Altera has provided video component blocks but video processing is very much a system design problem rather than a component design problem.  Jake

[Altera_Forum]

:) Hi Jake 

In answer to your questions 1. Its Scaler V9 and Quartus II v9 2. Cyclone 2 grade 7 3. I can display a static 720x288 RGB Image (16 bit Ram to resampler to colorspace converter to fifo to display, all homemade except the fifo - Altera megafunction fifo) 4. DRAM 16 bit databus running at 100MHz (Homemade controller) 5. Dual Clock fifo..100MHz in 50MHz out 1024 words deep 6. I'm using nearest neighbour at the moment just because it compiles quicker, I've used a 1:1 scale ratio and got a stable image but I need 800x600 7. The output block is homemade running at 50MHz i.e. vga 800x600x72Hz 8. There is no fifo between the scaler and output 9. I dont send any control packets for resolution, I assumed that the Megafunction wizard would've sorted it out..:)  10. Theres nothing in the output path to remove control packets but I only send startofpacket and endofpacket   I've included counters in the vga sync generator section to give 1 pulse a pixel before the frame starts and then give another pulse as the frame ends, I detect these pulses and send the startofpacket, endofpacket signals. Then I enable the fifo output and send the 24 bit data to the scaler. The din_ready output of the scaler is checked before any of the above is allowed.   I've connected the output enable of the scaler to Vcc and also to a VGA_Active_Area signal, both give the same result.   This is the system as it stands at the moment...There have been other manifestations with various different timing scenarios, none of which worked lol   Thanks for your response Peter

[Altera_Forum]

Well the easiest thing would be for me to see your design but here are some things that worry me. 

 1 - Are you aware of and properly handling the ready_latency value of 1 on the scaler's avalon streaming ports? This means that when it asserts din_ready, you present valid data on the next clock cycle. Likewise, when you assert dout_ready, it presents valid data on the following clock cycle. 2 - I don't know if the scaler will operate properly without control packets on the input. I think it will use whatever settings you specified in the megawizard but I've never tried it. 3 - My understanding is that the scaler will put control packets on the output regardless of whether or not they are present on the input. If so, you will have to either ignore or remove these. 4 - For video packets going into the scaler, the data accompanying the startofpacket signal must be a value of zero. This is not part of the actual video data but instead a flag to indicate to the scaler that this particular packet is video data. Similarly, the scaler's output will be in the same format. 5 - I think you should have an elastic line buffer (FIFO) between the scaler and your output. 6 - Obviously you can't tie the dout_ready signal on the scaler to vcc. You need to pull the data out as dictated by output timing.  Do any of these sound like things you need to check or are you covering all of this already?  Jake

[Altera_Forum]

Hello again 

I've got most of the issues you described sorted, I wasnt aware that the scaler outputs control packets though. Do you know when the packets are sent? I'm pretty sure that the control packets dont need to be sent to the scaler, they are handled when you set up the megawizard. I'll include code in the output block to ignore packets but it'll have to wait until tomorrow....its 22:45 in Wales :)    Thanks again for replying

[Altera_Forum]

Control packets are placed in the stream before the actual video packet. In general you should not assume that there will only be one control packet as most of the VIP will propogate packets from upstream blocks. The last control packet preceding the video packet contains the information pertaining to the video packet. 

 As this is really a pretty trivial component, I'm going to give you the attached module. Sorry it's in Verilog, I know how fond Europeans are of "Very Hard Description Language." :) Basically the component just removes and packets from the stream that are not video packets. It also (*MAKE NOTE*) removes the leading zero from the video packet. So all you are left with is the raw video data. The startofpacket and endofpacket signals coincide with the first and last pixels of the frame respectively.  Jake