FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
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VIP: clocked video input, frame buffer and clocked video output

Honored Contributor II

I am using the tPad development board from Terasic. 

The CCD outputs 1920 x 1080 @ 30fps, clocked with 96MHz. 

The video then enters the SOPC etc. 


As a reference, I want also to see the original video on the big LCD that is 800 x 600 clocked with 40MHz. 


There is the Terasic's reference design (tpad_Camera) that has a custom frame (no SOPC) buffer but that buffer is written specifically for 800 x 600 @ 50Mhz input video. It is badly documented and I have given up trying to understand, modify and reuse it. 


Instead, I came to idea that seemed quite genious :-) Let's have Clocked Video Input, Frame Buffer, and Clocked Video Output in my SOPC, next to the rest of the system. 


As the first step, I took a look at another Terasic's demo (tPad_VIP_camera) that employs the three mentioned IP's beside many other from VIP suite. It takes video from the camera and outputs its transformed version at the big LCD. The IP's are parametrizable and that's cool. First I wanted to verify the concept, so I kept 800 x 600 @ 50MHz video, connected it to Clocked Video Input, then Frame Buffer, then Clocked Video Output that drives the LCD. Should work, but it does not. 

I have no software control over these cores, I expect them to work in default mode (parameters) which I copied from the Terasic demo that works like charm. 


Am I missing something here? I think my questions are: 

- is a component missing in this video path? 

- could I have Clocked Video Input, Frame Buffer, and Clocked Video Output working in the desired mode after power up without software intervention? 


Many thanks in advance
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Honored Contributor II

The case is closed. 

Some notes for people stumbling upon a similar issue: 

Different CCD's and the display's clock and frame rates could cause problems. Give a try to "frame repetition" and "frame dropping" options in Frame Buffer component. 

You could have a software control of component's parameters, but shoulould be fine wihtout Avalon MM control port in case your input and output resolutions are fixed. In that case, the IP's are running just after power-up and with the default parameters. The CVI will work with the resolutions up to the default one, that is id the default is 1920 x 1080 it will also work for 800 x 600 and so on. 

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