FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP

VIP interlacer block

Honored Contributor II

Has anyone been successful in creating 1080i output from the Clocked Video Output -block with external syncs? 


I've been trying to build several simple test interface systems consisting of a test pattern generator and CVO block configured as 1080i60 interlaced with trial-and-error setting of timing parameters. I've also used the Interlacer megafunction with a 1080p signal feeding it from a TPG.  

There doesn't seem to be any documentation regarding the proper timings values and just by looking 1080i timings from CEA861 is confusing as it says the second field starts at the middle of the line number 563. There doesn't seem to be a way to use 563.5 lines.. 


Anyone with any insight?
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