FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP

VIP switch clocking

Honored Contributor II

I'm using the VIP Switch and am starting to have trouble controlling it correctly. After some digging I noticed that the Switch block only has a single clock despite having both a MM and ST interfaces. We recently bumped up our MM bus speed after which we noticed the lack of control. 


Is the control interface to the Switch running on the ST clock? (This would be hidden in the reference designs since the video clock drives the CPU as well.) Or is the clock supposed to be connected to the CPU clock and not the ST clock because the block is a transparent switch? The documentation is unclear as to which clock it is.
0 Kudos
0 Replies