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Hi
1) Is there option to define which VREF the FPGA use ? (interal FPGA vref or external IO pin )
If yes - where should I define it in the Quartus
2)Do all the banks should get same vref ?
3)How can I make same vref value when I transfer SERDES data from FPGA to other ( each FPGA locate in other board)
Yishay
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Hello,
May I know which FPGA are you using?
Thank you.
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Hi
DEVICE 1SG10MHN3F74C2LG_U1
FAMILY "Stratix 10"
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Hello Yishay,
Hope you are doing well. You can define Vref by using Pin Planner in your Quartus. There is an external VREF pin for every I/O bank, providing one external VREF source for all I/Os in the same bank. You can refer to page 40 from Stratix 10 GPIO User Guide
Additional documents that you can refer to is as below:
1. Intel Stratix 10 Device Datasheet
Thank you.
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Hi
Thank you for your answer ,
According to the DS there is option to choose which VREF to use , internal or exteranal
Attached screenshot :
But , I dont find any option choose it in the Pin Planner :
Please advise
Yishay
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Hello,
When you click on that GUI in the Pin Planner it will show you the pin location on tab on your right. You can set your fitter location to that pin at the bottom of the Pin Planner GUI.
Thank you.
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We do not receive any response from you to the previous question/reply/answer that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.

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