1) Is there option to define which VREF the FPGA use ? (interal FPGA vref or external IO pin )
If yes - where should I define it in the Quartus
2)Do all the banks should get same vref ?
3)How can I make same vref value when I transfer SERDES data from FPGA to other ( each FPGA locate in other board)
Hope you are doing well. You can define Vref by using Pin Planner in your Quartus. There is an external VREF pin for every I/O bank, providing one external VREF source for all I/Os in the same bank. You can refer to page 40 from Stratix 10 GPIO User Guide
Additional documents that you can refer to is as below:
We do not receive any response from you to the previous question/reply/answer that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.