Verilog basics - isolating a bit in a sum

Altera_Forum · ‎03-20-2012

Inside an always statement:

c <= a + b;

s <= c[7];

What if I wanted to do:

s <= (a+b)[7];

It does not work as such (compiler error), but it'd be convenient in that I do not want to store the result in a register and waste a clock cycle.

Is there a way to do something like this?

Thanks.

Altera_Forum · ‎03-20-2012

You can simply define s as a wire and use an assign statement

Altera_Forum · ‎03-20-2012

Huh that makes sense.

Thanks!