Video-over-IP on new Quartus

[Altera_Forum]

I am trying to implement a Video over IP design on Cyclone III. Did anyone manage to compile and successfully use the whole package on any FPGA? Would be great if someone responds who had success or failed. I am mostly interested in successful designs on Cyclone III, but others are OK too. This thread is rather a problem log for starters, so maybe it will be useful for further users. 

 System: Quartus 10.1sp1 Devboards (didn't choose the right one yet): Cyclone III Video Development Kit EP3C120 Cyclone III Starter Kit EP3C25 (should fit, since the ref design is on EP2C25) Cyclone III Nios board (Also known as NEEK) EP3C25 Reference design: VoIP-2.4.0 by AN374  (2011-03-25) Firstly I am trying to implement the reference design with no changes. a) The SOPC builder doesn't find the required IPs. Solution: 1. Create additional IP directory somewhere. E.g. C:\Altera\ip_cores. 2. Copy all the additional cores to that directory. 3. Open SOPC builder. 4. Go to Tools->Options...->IP Search Path. 5. Add a directory mentioned before. 6. The ethernet core drops an error, so choose the correct clock and connect to the bus. Fallow the advices on the SOPC message window.  b) The design fails dropping an error bacause of too small amount of M4K blocks. Solution:  Switch fitter optimization to area (didn't check balance) instead of speed.  c) The design fails dropping an error after successful synthesis, fitting and assembling: "Output clocks to SDRAM Not Found " Solution: 1) comment a line in %quartus_rootdir%\10_1\ip\altera\ddr_ddr2_sdram\lib\tcl\paths.tcl # ::ddr::extract::follow_edge2 mux async "~DELAY_CELL\$" found_tco "" failflag under extract_clk_tco procedure. Its in the end of the file. OR (a solution, which I did not test) 2) Remove the DDR constraint from the .qsf file.  So far, the design compilation runs fine. However, I can't test it on the real hardware.  Will be updated.  References: http://www.alteraforum.com/forum/showthread.php?t=4487 (http://alteraforums.net/forum/showthread.php?t=17764) http://alteraforums.net/forum/showthread.php?t=17764

[Altera_Forum]

Hi, 

I am taking over a design already implemented and making some changes. I have gotten the design into SOCP after overcoming the same issues you describe. I am using an external processor so I am not so sure how much use the SOCP ENV will be but I am interested in hearing how the development is going especially wrt testbench and checkers.  Separately the design seem to have a means of time multiplexing TS streams into channels. I would be real interested if this has been proven in general. and also with interleaving of the 2 TS streams on every 32-word bursts. I will start a different thread for this idea. Thx

[Altera_Forum]

That reference design never worked for me so I've given up and started my own from the very basics.

[Altera_Forum]

Hi,  

 I have successfully done the DVI 1080P Loop-through (Beta) which has DVi input and output and verified on cyclone 3 development board.It works fine.i had to modify the design from the original one from bitec, but now i am having problems using the vip suite from the altera..  can u help me with some design with DVI in -> vip suite processing -> DVi op  Its very urgent to me...

[Altera_Forum]

Check altera wiki, there are some examples.