Solved: Warning regarding ignored SDC when compiling PCIe design. - Intel Community

FPGA Intellectual Property

PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP

Warning regarding ignored SDC when compiling PCIe design.

557 Views

I running the compilation of PCIe avalon ST example design and get a lot of warning like below. Please help...

Warning(332174): Ignored filter at altera_xcvr_native_a10_false_paths.sdc

1 Solution

430 Views

Hi Sir,

These warning can be ignore. See this KDB link: https://www.intel.com/content/altera-www/global/en_us/index/support/support-resources/knowledge-base/ip/2019/why-does-intel-arria-10-and-intel-cyclone-10-avalon-st-or-avalon-mm-interface-for-pci-express-ip-example-design-issue-ignored-sdc-constraint-warnings.html

View solution in original post

Copy link

Link Copied

1 Reply

431 Views

Hi Sir,

These warning can be ignore. See this KDB link: https://www.intel.com/content/altera-www/global/en_us/index/support/support-resources/knowledge-base/ip/2019/why-does-intel-arria-10-and-intel-cyclone-10-avalon-st-or-avalon-mm-interface-for-pci-express-ip-example-design-issue-ignored-sdc-constraint-warnings.html

Copy link

Community support is provided Monday to Friday. Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.